Chip Design Enters The Third Dimension

TO ANALYZE A CHIP DESIGN with millions of transistors, today's best computer tools model the transistors only in two dimensions. Depth is ignored because the main action takes place at the surface of thin films on the silicon. But this will soon change. The width of the transistors is fast approaching the thickness of the surface films. This means the activity of electrons at the sides of a transistor will have to be modeled, too.

Simulating the 3D movements of electrons in millions of transistors requires a custom-built supercomputer costing almost $15 million. But in March, Robert W. Dutton, chief scientist at Stanford University's Center for Integrated Systems, reported that a research team has developed an algorithm that outperforms that custom computer more than fivefold--using versions of IBM's new POWERparallel SP-2 supercomputer costing half as much.

One setup can do 9.5 billion math operations a second. At such speeds, simulations in 3D won't take much longer than in 2D. And the improved accuracy of 3D models will better uncover problems during design, which could slash development time by months.

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