ducts, transistor-level extraction and device modeling tools, compute the values of detailed circuit parameters, including interconnect resistances, capacitances, and inductances to enable customers to simulate the performance of a design before it is manufactured. The Calibre Resolution Enhancement Technology (RET) tools allow wafer foundries to manipulate the light used to create ICs to make structures on the IC that are finer than would be possible with conventional exposures. The Calibre family of optical proximity correction (OPC), RET, and mask data preparation tools enable higher yields in semiconductor manufacturing. The Calibre OPCverify tool is used to check and report the effectiveness of mask pattern corrections against wafer manufacturing specifications. The Calibre RET tools continue to be extended to provide computational patterning capabilities for process technology nodes from 130 nm to 7 nm. In the Design For Manufacturing (DFM) area, the Calibre LFD product could help customers produce higher yields at nm process geometries where variations in manufacturing could cause yield reductions. The Calibre CMPAnalyzer tool allows customers to model the expected planarity (thickness variation) of ICs and identify where modifications to the layout would improve a chip’s flatness. This helps prevent manufacturing defects and reduces variations in performance from one chip to the next. The Calibre MPCpro product is a solution for systematic errors introduced by e-beam lithography and mask etching processes built on Calibre OPCpro technology for optical process correction. The company’s Calibre nmMPC product provides optimizations primarily developed for e-beam mask writers. The Calibre PERC tool checks the electrical design of an IC. It is useful in verifying the completeness of electrostatic discharge protection circuitry, which affects both manufacturing yield and long-term reliability of an IC. The company’s Tessent suite of integrated silicon test products are used to test a design's logic and memories after manufacturing to ensure that a manufactured IC is functioning correctly. Its suite of tools includes scan insertion, boundary scan, automatic test pattern generation, logic and memory built-in self-test, and its patented Tessent TestKompress product for EDT (Embedded Deterministic Test). A suite of test analysis products is also available that leverages test data and layout-aware diagnosis capabilities for silicon debug and yield analysis. For customers designing ICs at advanced nodes, the company offers the Olympus-SoC place and route product. The Olympus-SoC system comprehensively addresses the performance, capacity, time-to-market, power, and variability challenges encountered at the process geometries. The Olympus-SoC place and route solution is a physical design implementation tool, which performs design planning, placement, physical synthesis, clock tree synthesis, routing, power optimization, and manufacturability closure. The Olympus-SoC tool is architected to handle the complex multi-patterning and FinFET requirements at advanced process technologies. The Calibre InRoute design and verification platform enables designers to increase their productivity by invoking Calibre tools within the Olympus-SoC place and route environment. The company also offers the Oasys-RTL synthesis tool to include register-transfer level (RTL) synthesis in its digital implementation flow. The Oasys-RTL solution helps SoC and ASIC design teams to realize improved quality of results and faster turnaround time for complex SoCs, ASICs, and IP blocks. The Oasys-RTL tool’s ‘placement first’ synthesis methodology and integrated RTL floorplanning capability enable physical backend issues to be analyzed and addressed at RTL stages before hand-off to back-end groups for physical design implementation. In 2016, the company acquired the Tanner EDA tool suite, which facilitates the design, layout, and verification of analog/mixed signal and MEMS (micro-electro-mechanical systems). Integrated System Design The company’s PCB-FPGA Systems Design software products support the PCB design process from schematic en
mentor graphics corp (MENT:NASDAQ GS)
8005 S.W. Boeckman Road
Wilsonville, OR 97070
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