Xilinx and BEEcube Announce Highly Scalable Prototyping Platform for 5G Massive Mimo Antenna Systems
Feb 25 15
Xilinx Inc. announced a highly scalable prototyping platform for 5G massive MIMO antenna systems. The new MegaBEE prototyping platform
supports up to 256x256 antennas and provides all the elements necessary to put a massive MIMO system on the air within LTE bands and without external hardware. The MegaBEE platform's unique clocking structure allows antenna modules to be dispersed over a three mile radius while maintaining phase coherence, enabling the system to be used for distributed MIMO as well as massive MIMO systems with greater coverage and capacity. Included in the MegaBEE platform are RF chains, filters, power amps, 4000 parallel DSP slices, processor cores, multiple channels of 10GE interconnect, and on-board DDR3 memory for storing real-time 5G test vectors. In addition, Xilinx's Zynq All Programmable SoCs enable the massive compute bandwidth demanded by massive MIMO algorithms with an architecture featuring high-speed logic fabric, DSP blocks, Block RAM capable of running 491MHz+, and SERDES able to run at up to 12.5Gbps. The Zynq SoC's dual-core ARM® Cortex® A9 MPCores enable a Linux cluster architecture unique in the 5G prototyping space. MegaBEE also fully integrates with the Xilinx® Vivado® tool suite to significantly reduce development time for early 5G systems, while providing a library of IP to implement all inter-chip communication.
Xilinx and Xylon Announces Automated Multi-Camera Image Stitching IP for 2D/3D Surround View Systems
Feb 24 15
Xilinx Inc. and Xylon announced new automated multi-camera image stitching IP for 2D/3D surround view systems. The Automotive logiADAK 3.0 Advanced Driver Assistance Development Kit with logiOWL IP enables on-target, full vehicle level multi-camera calibration in seconds for Tier One automotive electronics suppliers and OEM automakers. The new logiOWL IP in the logiADAK 3.0 Automotive Driver Assistance Kit is based on the Zynq® All Programmable SoC which improves design accuracy, reduces manufacturing costs due to manual calibration process, and decreases time on final test and validation. The logiOWL-based Auto calibration runs fully embedded in the vehicle and enables full vehicle level multi-camera calibration in as little as 10 seconds. The multi-camera calibration process does not require a complex calibration site, is simple and inexpensive, and can be easily executed in repair shops without specialized training. The Automotive logiADAK 3.0 Advanced Driver Assistance Development Kit with automated calibration includes, 360 degree surround view with 3D and bird's eye viewing modes using up to six cameras, enabling the rapid development for larger vehicles including commercial trucks, rear-view camera with a wide array of customizable viewing modes, including rear cross path indicators, pedestrian detection with tracking capability for forward camera collision avoidance, lane departure warning, blind spot detection using optical flow, and face detection and tracking. The logiADAK 3.0 Advanced Driver Assistance Development Kit is now available through Xylon.
Xilinx, Inc. Announces its 16nm UltraScale+ Family
Feb 23 15
Xilinx Inc. announced its 16nm UltraScale+ family of FPGAs, 3D ICs, and MPSoCs, combining new memory, 3D-on-3D and multi-processing SoC (MPSoC) technologies, delivering a generation ahead of value. In addition, to enable an even higher level of performance and integration, the UltraScale+ family also includes a new interconnect optimization technology, SmartConnect. These devices extend Xilinx's UltraScale portfolio ‘ now spanning 20nm and 16nm FPGA, SoC, and 3D IC devices ‘ and leverage a significant boost in performance/watt from TSMC's 16FF+ FinFET 3D transistors. Optimized at the system level, UltraScale+ delivers value far beyond a traditional process node migration ‘ providing 2 ‘5X greater system level performance/watt over 28nm devices, far more systems integration and intelligence, and the high level of security and safety. The new Xilinx UltraScale+ FPGA portfolio is comprised of Xilinx's Kintex ® UltraScale+ FPGA and Virtex ® UltraScale+ FPGA and 3D IC families, while the Zynq ® UltraScale+ family includes the industry's first all programmable MPSoCs. With this portfolio, Xilinx addresses a broad range of next generation applications, including LTE Advanced and early 5G wireless, terabit wired communications, automotive ADAS, and industrial Internet-of-Things (IoT). Memory Enhanced Programmable Devices: UltraRAM attacks one of the large bottlenecks affecting FPGA- and SoC-based system performance and power by enabling SRAM integration. The new technology can be leveraged to create high capacity on-chip memory for a variety of use cases ‘ including deep packet and video buffering ‘ providing predictable latency and performance. By integrating massive amounts of embedded memory very close to the associated processing engines, designers can achieve greater system performance/watt and BOM cost reduction. UltraRAM scales up to 432 Mbits in a variety of configurations. SmartConnect Technology:SmartConnect is a new and innovative interconnect optimization technology for FPGAs. It provides additional 20% to 30% performance, area, and power advantages through intelligent system-wide interconnect optimization. While the UltraScale architecture attacks the silicon-level interconnect bottleneck through re-architected routing, clocking, and logic fabric, SmartConnect applies interconnect topology optimizations to match design-specific throughput and latency requirements while reducing interconnect logic area. Industry's First 3D-on-3D Technology: The high end of the UltraScale+ portfolio leverages the combined power of 3D transistors and third generation of Xilinx 3D ICs. Just as FinFETs enable a non-linear improvement in performance/watt over planar transistors, 3D ICs enable a non-linear improvement in systems integration and bandwidth/watt over monolithic devices. Heterogeneous Multi-processing Technology: The new Zynq UltraScale+ MPSoCs include all of the aforementioned FPGA technologies with an unprecedented level of heterogeneous multi-processing, deploying the ‘the right engines for the right tasks.’ These new devices deliver approximately 5X system level performance/watt relative to previous alternatives. At the center of the processing-subsystem is the 64-bit quad-core ARM ® Cortex ®-A53 processor, capable of hardware virtualization, asymmetric processing, and full ARM TrustZone ® technology support. The processing sub-system also includes a dual-core Cortex-R5 processor for real-time deterministic operation, ensuring responsiveness, high throughput, and low latency for the high levels of safety and reliability. A separate security unit enables military-class security solutions such as secure boot, key and vault management, and anti-tamper capabilities ‘ standard requirements for machine-to-machine communication and industrial IoT applications. For complete graphics acceleration and video compression/decompression, the new devices incorporate an ARM Mali ¢-400 graphics processor as well as a H.265 video codec unit, combined with support for Displayport, MIPI and HDMI. Finally, a dedicated platform and power management unit (PMU) has been added to support system monitoring, system management, and dynamic power gating for each of the processing engines. Early customer engagements are in process for the UltraScale+ families. First tape out and early access release of the design tools are scheduled for the second calendar quarter of 2015. First ship is scheduled for the fourth calendar quarter of 2015.