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Last €39.19 EUR
Change Today -0.081 / -0.21%
Volume 60.0
XIX On Other Exchanges
Symbol
Exchange
Mexico
Frankfurt
As of 3:23 PM 07/6/15 All times are local (Market data is delayed by at least 15 minutes).

xilinx inc (XIX) Snapshot

Open
€39.01
Previous Close
€39.27
Day High
€39.45
Day Low
€38.92
52 Week High
05/28/15 - €44.79
52 Week Low
10/14/14 - €28.32
Market Cap
10.1B
Average Volume 10 Days
61.6
EPS TTM
--
Shares Outstanding
258.7M
EX-Date
05/11/15
P/E TM
--
Dividend
€1.23
Dividend Yield
2.51%
Current Stock Chart for XILINX INC (XIX)

xilinx inc (XIX) Related Businessweek News

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xilinx inc (XIX) Details

Xilinx, Inc. designs and develops programmable devices and associated technologies worldwide. Its programmable devices comprise integrated circuits (ICs) in the form of programmable logic devices (PLDs), such as programmable system on chips, and three dimensional ICs; software design tools to program the PLDs; targeted reference designs; printed circuit boards; and intellectual property (IP), which consists of Xilinx and various third-party verification and IP cores. The company also offers legacy development boards; development kits, including hardware, design tools, IP, and reference designs that are designed to streamline and accelerate the development of domain-specific and market-specific applications; and configuration products, such as one-time programmable and in-system programmable storage devices to configure Xilinx field programmable gate arrays. In addition, it provides design services, customer training, field engineering, and technical support. The company offers its products to electronic equipment manufacturers in end markets, such as wired and wireless communications, industrial, scientific and medical, aerospace and defense, audio, video and broadcast, consumer, automotive, and test and measurement. Xilinx, Inc. sells its products through a network of independent distributors; and through direct sales to original equipment manufacturers by a network of independent sales representative firms and by a direct sales management organization. The company was founded in 1984 and is headquartered in San Jose, California.

3,451 Employees
Last Reported Date: 05/13/15
Founded in 1984

xilinx inc (XIX) Top Compensated Officers

Chief Executive Officer, President and Direct...
Total Annual Compensation: $787.5K
Chief Financial Officer and Executive Vice Pr...
Total Annual Compensation: $480.0K
Senior Vice President of Global Operations & ...
Total Annual Compensation: $381.7K
Executive Vice President and General Manager ...
Total Annual Compensation: $480.0K
Senior Vice President and General Manager of ...
Total Annual Compensation: $370.4K
Compensation as of Fiscal Year 2015.

xilinx inc (XIX) Key Developments

Xilinx Inc. Announces All Programmable Multi-Processor SoC

Xilinx Inc. announced the All Programmable Multi-Processor SoC (MPSoC) using TSMC's 16FF+ process, targeting embedded vision, including ADAS and the path to autonomous vehicles, Industrial Internet of Things (I-IoT), and 5G wireless systems. The All Programmable Zynq® UltraScale+™ MPSoC enables the development of flexible, standards-based platforms by providing 5X system level performance/watt and any-to-any connectivity with the security and safety required for next generation systems. This heterogeneous multi-processing SoC, the new device combines seven user programmable processors including a quad-core 64-bit ARM® Cortex™-A53 Application Processing Unit, a dual-core 32-bit ARM® Cortex™-R5 Real Time Processing Unit, and an ARM® Mali™-400 Graphics Processing Unit. The Zynq UltraScale+ MPSoC family also includes a host of integrated peripherals, safety and security features, and advanced power management. When coupled with the recently introduced SDSoC™ development environment, the new family is enabling systems that are both software defined and hardware optimized. Enabling Embedded Vision Including ADAS, Industrial IoT, and 5G Systems: the Zynq UltraScale+ MPSoC is tailored for next-generation embedded vision systems, including industrial machine vision, surveillance, and automotive ADAS systems. For ADAS, the Zynq MPSoC tightly couples highly parallelized hardware image processing and analytics acceleration with software based algorithm configuration and control. With the addition of expanded memory with UltraRAM™ for video buffering, throughput is maximized and latency is reduced; a critical attribute for ADAS. Finally, to enable real-time safety-critical countermeasure decisions and initiate actuator commands, the Zynq MPSoC ARM with dual core Cortex-R5 engines can be utilized in lockstep mode along with cross-monitoring and diagnostic-protected voting in the programmable fabric. The Zynq MPSoC was designed with automotive ISO-26262 functional safety requirements in mind, while still offering a scalable and highly customizable programmable platform that will future-proof customer designs in the quickly changing ADAS space. For the Industrial Internet of Things, the Zynq UltraScale+ MPSoC family is ideally suited to integrate data acquisition, perform real-time diagnostics, and enable local decision-making for intelligent connected control systems. The combination of the MPSoC processing subsystem, the UltraScale programmable logic fabric, and the new UltraRAM on-chip memory technology create the ideal platform to process the vast quantities of data for analytics and manage real-time machine-to-machine (M2M) communication. With a dedicated security processing unit and dual core Cortex-R5 engines that can be configured for lockstep, the Zynq MPSoC also supports SIL3 functional safety and security requirements. Zynq UltraScale+ MPSoC devices support the increased radio and baseband processing requirements of next generation 5G systems. This includes the support of new 'massive MIMO' and adaptive beamforming architectures, CloudRAN layer 1 baseband acceleration and associated Fronthaul applications, with flexible support of multiple standards and multiple bands at significantly lower power. The Zynq UltraScale+ MPSoC, with its quad core ARM Cortex-A53 processing subsystem, leverages an integrated fine grain power management system to implement lower power optimal hardware-software design for digital pre-distortion, beamforming control functions, and system management tasks.

Xilinx Inc. and China Mobile Research Institute Collaborate on Next Generation Fronthaul Interface Development for 5G Wireless Networks

Xilinx Inc. announced its collaboration with China Mobile Research Institute (CMRI) for the development of the next generation fronthaul interface (NGFI) in an MOU. With the advent of 5G wideband multi-antenna systems, Xilinx and CMRI are working together to research the key technologies and components of a new fronthaul interface for wireless networks, in conjunction with emerging technologies such as C-RAN, large-scale-antenna-system, and 3D MIMO. In current wireless systems, the bandwidth of CPRI has increased rapidly and requires more and more fiber cables to be laid by the operators. This is costly and very challenging for the centralized baseband architecture, which is the trend for future wireless networks. The fronthaul link, between the baseband and radio units, is a critical subsystem for improvement. Xilinx All Programmable devices and design environments will serve as an important enabler for this interface and future wireless systems. Xilinx is contributing to the NGFI eco-system with a validated NGFI reference design on its Zynq® SoC platform. The reference design, which can easily be migrated to other Zynq and Zynq UltraScale+ MPSoC devices, will serve as a baseline framework for 4.5G/5G wireless network research.

Xilinx, Inc. Announces the 2015.1 Release of the Sdaccel Development Environment for OpenCL Framework, C and C++

Xilinx Inc. announced the 2015.1 release of the SDAccel development environment for OpenCL framework, C, and C++. The SDAccel development environment is a member of the SDx family of development environments for systems and software engineers, enabling up to 25X better performance/watt for data center application acceleration leveraging FPGAs. This new release enhances the SDAccel integrated development environment (IDE), extends OpenCL standard compliance, and features an expanded ecosystem of SDAccel development environment-certified Alliance Members providing platforms, libraries, and design services. The SDAccel development environment 2015.1 release provides new ease-of-use enhancements to the Eclipse-based SDAccel IDE including new debug and profiling features to accelerate the development and deployment of OpenCL, C, and C++ kernels. In addition, the release expands on SDAccel development environment Khronos standard compliance with support for a new OpenCL Installable Client Driver (ICD). With the ICD extension, multiple implementations of OpenCL can co-exist on the same system, enabling applications developers to select real-time between CPUs, GPUs and FPGAs for run time acceleration and power savings.

 

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