Last $42.99 USD
Change Today -0.75 / -1.71%
Volume 792.8K
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As of 8:10 PM 01/30/15 All times are local (Market data is delayed by at least 15 minutes).

synopsys inc (SNPS) Snapshot

Open
$43.51
Previous Close
$43.74
Day High
$43.88
Day Low
$42.94
52 Week High
12/4/14 - $45.03
52 Week Low
04/15/14 - $36.03
Market Cap
6.6B
Average Volume 10 Days
652.5K
EPS TTM
$1.61
Shares Outstanding
153.1M
EX-Date
--
P/E TM
26.6x
Dividend
--
Dividend Yield
--
Current Stock Chart for SYNOPSYS INC (SNPS)

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synopsys inc (SNPS) Details

Synopsys, Inc. provides electronic design automation (EDA) software products used to design and test integrated circuits and electronic systems in the United States, Europe, Japan, and the rest of Asia Pacific. Its EDA solutions include Galaxy Design platform that provides integrated chip design solution; Verification Continuum Platform, which offers virtual prototyping, static and formal verification, simulation, emulation, field-programmable gate array (FPGA)-based prototyping, and debug; and FPGA design products that are complex chips customized or programmed to perform specific functions. The company also offers DesignWare intellectual property (IP) solutions that comprise solutions for interfaces, such as USB, PCI Express, DDR, Ethernet, SATA, and HDMI; analog IP for analog-to-digital data conversion, audio, and video; and system-on-chip (SoC) infrastructure IP, including minPower datapath components, ARM AMBA interconnect fabric and peripherals, and verification IP. In addition, it provides logic libraries and embedded memories; configurable processor cores and application-specific instruction-set processors for embedded and deeply embedded designs; and IP subsystems for audio and sensor functionality. Further, the company offers Platform Architect software that enables exploration of SoC architectural trade-offs; SPW and System Studio tools for algorithm design; Processor Designer software for custom processor design; Synphony Model and C Compiler for high-level synthesis; Virtualizer tool and transaction-level models to create virtual prototypes and functional software models; and HAPS FPGA-based prototyping systems. Additionally, it provides software quality, testing, and security tools; manufacturing solutions that enable semiconductor manufacturers to develop fabrication processes; and consulting and design services for various phases of SoC development process. The company was founded in 1986 and is headquartered in Mountain View, California.

9,436 Employees
Last Reported Date: 12/15/14
Founded in 1986

synopsys inc (SNPS) Top Compensated Officers

Co-Chief Executive Officer, President and Dir...
Total Annual Compensation: $500.0K
Co-Founder, Chairman and Co-Chief Executive O...
Total Annual Compensation: $500.0K
Chief Administrative Officer and Executive Vi...
Total Annual Compensation: $400.0K
Executive Vice President of Worldwide Sales &...
Total Annual Compensation: $480.0K
Compensation as of Fiscal Year 2013.

synopsys inc (SNPS) Key Developments

Synopsys, Inc. Announces the Availability of the New DesignWare® Medium Density Non-Volatile Memory IP Family

Synopsys Inc. announced the availability of the new DesignWare® Medium Density Non-Volatile Memory (NVM) IP family. The Medium Density NVM IP fills the gap between lower bit count NVM and flash memory, without requiring additional masks or processing steps, reducing die cost by up to 25%. The Medium Density NVM IP provides up to 64 Kbytes of on-chip memory and eliminates the need for external EEPROM or flash memory when integrating microcontrollers in analog IC designs for smart sensors, power management and touchscreen controller applications. The DesignWare Medium Density NVM IP products bring flash functionality to 5V CMOS and BCD process technologies, where embedded reprogrammable NVM is needed. Error checking and correction functionality provides additional system reliability and reduces implementation efforts. The NVM IP delivers more than 5X the density compared to lower bit-count NVM solutions and offers 40 nanoseconds access time, providing fast read times and real-time computing. Validated through rigorous characterization, qualification and reliability testing in Synopsys labs, the NVM IP supports temperature ranges from -40°C to 125°C with 10 years of data retention. The DesignWare Medium Density NVM IP is available now to early adopters in TSMC 180-nanometer (nm) 5V CMOS and BCD process technologies.

Rockchip Electronics Co., Ltd. Selects Synopsys, Inc.'s DesignWare IP for Mobile Application Processor SOC

Synopsys Inc. has announced that Fuzhou Rockchip Electronics Co. Ltd. has selected Synopsys's DesignWare IP portfolio for its mobile application processor system-on- chip, or SoC. Rockchip selected Synopsys' DesignWare IP because of its high quality and strong combination of low power, high performance and small area, which is critical to meet the requirements of the mobile market.

Synopsys Expands Memory Verification IP Portfolio with UFS, UniPro and eMMC to Accelerate Verification Closure for Mobile Designs

Synopsys Inc. announced the expansion of its memory Verification IP (VIP) portfolio to include key titles for the mobile industry. Synopsys memory VIP is based on a native SystemVerilog architecture to enable enhanced ease of use, integration and configurability. With these advanced features, project teams using the JEDEC UFS, MIPI® UniProSM and JEDEC eMMC protocols can further accelerate verification closure of mobile block, subsystem and system-on-chip (SoC) designs. VIP for the emerging UFS and UniPro protocols also includes self-contained compliance test suites to accelerate verification closure and eliminate the tasks of developing a verification environment and tests. The test suites are delivered as native SystemVerilog source code for improved reuse, extensibility and debug. The JEDEC eMMC VIP includes support for eMMC Card and Host. All verification IP and test suites are based on a consistent SystemVerilog UVM architecture to enable easy adoption. The company’s broad portfolio of bus, interface and memory VIP includes built-in coverage and verification plans to enable coverage closure. It also includes support for Verdi® Protocol Analyzer to provide protocol-aware debug. Synopsys VIP for the JEDEC UFS, MIPI UniPro and JEDEC eMMC memory protocol specifications provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification convergence. Availability: Synopsys Verification IP for UFS, MIPI UniPro and eMMC are available standalone and as part of the Synopsys VIP Library as well as in the Verification Compiler™ product. The Synopsys DesignWare® digital controllers for UFS, MIPI UniPro and eMMC are also available now.

 

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Valuation SNPS Industry Range
Price/Earnings 26.2x
Price/Sales 3.3x
Price/Book 2.2x
Price/Cash Flow 17.1x
TEV/Sales 2.7x
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