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Last €17.98 EUR
Change Today +0.51 / 2.90%
Volume 0.0
CDS On Other Exchanges
Symbol
Exchange
NASDAQ GS
Frankfurt
As of 3:44 PM 05/22/15 All times are local (Market data is delayed by at least 15 minutes).

cadence design sys inc (CDS) Snapshot

Open
€17.70
Previous Close
€17.47
Day High
€17.98
Day Low
€17.57
52 Week High
04/10/15 - €18.28
52 Week Low
06/4/14 - €11.95
Market Cap
5.3B
Average Volume 10 Days
0.0
EPS TTM
--
Shares Outstanding
292.7M
EX-Date
--
P/E TM
--
Dividend
--
Dividend Yield
--
Current Stock Chart for CADENCE DESIGN SYS INC (CDS)

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cadence design sys inc (CDS) Details

Cadence Design Systems, Inc. develops, sells, leases, and licenses electronic design automation (EDA) software, emulation and prototyping hardware, verification intellectual property (VIP), and design intellectual property (design IP) for semiconductor and electronics systems industries worldwide. It offers functional verification products, including logic verification software that enables customers to coordinate verification activities across multiple teams and various specialists for verification planning and closure; and system design and verification products for hardware-software verification, as well as for system power exploration, analysis, and optimization. The company also provides digital integrated circuits (ICs) design products, such as logic design products for chip planning, design, verification, and test technologies and services; physical implementation products for use in place and route, signal integrity, optimization, and double patterning preparation; and signoff products to signoff the design as ready for manufacture by a silicon foundry, as well as design for manufacturing products for use in the product development process. In addition, it offers custom IC design and verification products to create schematic and physical representations of circuits down to the transistor level for analog, mixed-signal, custom digital, memory, and RF designs; and system interconnect design products to develop printed circuit boards and IC packages. Further, the company provides design IP products consisting of pre-verified and customizable functional blocks to integrate into customer’s SoCs; and VIP and memory models for use in system-level verification to model correct behavior of full systems interacting with their environments. Additionally, it offers engineering, methodology, education, and hosted design solutions, as well as technical support and maintenance services. The company was founded in 1988 and is headquartered in San Jose, California.

6,100 Employees
Last Reported Date: 02/20/15
Founded in 1988

cadence design sys inc (CDS) Top Compensated Officers

Chief Executive Officer, President, Director ...
Total Annual Compensation: $650.0K
Chief Financial Officer and Senior Vice Presi...
Total Annual Compensation: $400.0K
Executive Vice President and General Manager ...
Total Annual Compensation: $412.5K
Senior Vice President and General Manager of ...
Total Annual Compensation: $375.0K
Chief of Staff to the Chief Executive Officer...
Total Annual Compensation: $375.0K
Compensation as of Fiscal Year 2014.

cadence design sys inc (CDS) Key Developments

Cadence Design Systems Inc. Unveils Allegro® 16.6 Portfolio

Cadence Design Systems Inc. unveiled the Allegro® 16.6 portfolio, which features several new products and technologies. Included in this release is the new Allegro PCB Designer Manufacturing Option, which can shorten the time to create manufacturing documentation by up to 60%, and several key technology updates catered to increase efficiency, control and productivity for designers, while streamlining handoff to manufacturing. Driven by increasing demands to provide a more predictable and shorter design cycle, the Allegro 16.6 portfolio includes more capabilities that accelerate routing and tuning for high-speed interfaces such as DDR3 and DDR4. The Allegro 16.6 portfolio includes new products to help PCB designers achieve maximum efficiency and productivity, while keeping cost of ownership low. These new products include: Allegro PCB Designer Manufacturing Option, a comprehensive, powerful, easy-to-use toolset that makes it efficient and cost effective for PCB designers to streamline the development of a release-to-manufacturing package for their products. It includes the Design for Manufacturing (DFM) Checker, Documentation Editor and Panel Editor modules. The Documentation Editor module can speed up overall fabrication documentation by up to 60%; Allegro Rules Developer and Checker, which allows users to develop custom fabrication and assembly rules to extend capabilities provided by Allegro PCB Designer and the Manufacturing Option. This tool provides a relational geometric verification language designed specifically for creating rules that are proprietary and custom to an original equipment manufacturer (OEM). The rules can be viewed and executed from the Allegro Constraint Manager, making it a single source for all design rules checks (DRCs) within a PCB. The Allegro 16.6 technology portfolio update offers multiple capabilities that boost turnaround time by shortening design cycles, accelerating timing closure and providing more editing control. These capabilities include: Adding return path vias while routing differential pairs, ensuring a ground current return path for differential pair vias; Updates to avoid coupling of high-speed signals to the FR-4 fabric weave, making it easy for designers to create off-angle routes based on user-defined parameters, accelerating the PCB layout process significantly; Adjusting spacing for signals in interfaces such as DDR3 and DDR4, allowing users to compress signals in high-density route areas, and to spread signals to avoid crosstalk between signals or make space for tuning; A new shape-editing AppMode, allowing users to create and modify complex shape geometries very easily and quickly for copper shapes, flex cover lay geometries and complex pad shapes.

Cadence Design Systems Inc. Presents at 43rd Annual J.P. Morgan Global Technology, Media and Telecom Conference, May-18-2015

Cadence Design Systems Inc. Presents at 43rd Annual J.P. Morgan Global Technology, Media and Telecom Conference, May-18-2015 . Venue: The Westin Boston Waterfront, 425 Summer St., Boston, MA 02210, United States.

Cadence Design Systems Inc.'s USB 3.0 Host IP Solution for TSMC's 16nm FinFET Plus Process Pass USB-IF Compliance Testing and Receive USB-IF Certification

Cadence Design Systems Inc. announced that its USB 3.0 host IP solution for TSMC's 16nm FinFET Plus (16FF+) process is one of the first to pass USB-IF compliance testing and receive USB-IF certification. The complete controller and PHY integrated solution is pre-verified, which enables designers to mitigate project risk and reduce system-on-chip (SoC) integration and verification time. Cadence offers a complete USB 3.0 solution including the controller, PHY and verification IP. The certified USB 3.0 host solution for 16FF+ features an innovative architecture developed by FinFET design experts within Cadence and offers a 40% reduction in dynamic power consumption versus previous generations of the IP on other process nodes. To achieve this power reduction, the integrated USB host xHCI controller and PHY IP utilize power and clock gating in order to conserve energy as the USB protocol goes into a low-power sub-state. Additionally, the PHY is optimized to ease integration. With a reduced pinout, there are fewer combinations to verify and less complexity with fewer complex software interactions that need to be tested and debugged.

 

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CDS

Industry Average

Valuation CDS Industry Range
Price/Earnings 37.8x
Price/Sales 3.5x
Price/Book 4.3x
Price/Cash Flow 31.0x
TEV/Sales 2.6x
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