Last €15.81 EUR
Change Today +0.013 / 0.08%
Volume 0.0
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Exchange
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As of 3:19 PM 01/30/15 All times are local (Market data is delayed by at least 15 minutes).

cadence design sys inc (CDS) Snapshot

Open
€15.87
Previous Close
€15.80
Day High
€16.00
Day Low
€15.75
52 Week High
01/27/15 - €16.44
52 Week Low
02/7/14 - €10.01
Market Cap
4.6B
Average Volume 10 Days
90.0
EPS TTM
--
Shares Outstanding
292.7M
EX-Date
--
P/E TM
--
Dividend
--
Dividend Yield
--
Current Stock Chart for CADENCE DESIGN SYS INC (CDS)

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cadence design sys inc (CDS) Details

Cadence Design Systems, Inc. develops, sells or leases, and licenses electronic design automation (EDA) software, emulation hardware, verification intellectual property (VIP), and design intellectual property (design IP) for semiconductor and electronics systems companies worldwide. It offers functional verification products, including logic verification software that enable customers to coordinate verification activities across multiple teams and various specialists for verification planning and closure; system design and verification products for hardware-software verification, as well as for system power exploration, analysis, and optimization; design IP products consisting of pre-verified, customizable functional blocks to integrate into customer’s SoCs; and VIP and memory models for use in system-level verification to model correct behavior of full systems interacting with their environments. The company also provides custom integrated circuits (ICs) design and verification products to create schematic and physical representations of circuits down to the transistor level for analog, mixed-signal, custom digital, memory, and RF designs. In addition, the company provides digital IC design products, such as logic design products for chip planning, design, verification, and test technologies and services; physical implementation products, which are used in place and route, signal integrity, optimization, and double patterning preparation; and signoff products to signoff the design as ready for manufacture by a silicon foundry. Further, it offers system interconnect design products to develop printed circuit boards and IC packages; and design for manufacturing products to address manufacturing and yield issues in the product development process. Additionally, the company offers engineering, methodology, education, and hosted design solutions. Cadence Design Systems, Inc. was founded in 1988 and is headquartered in San Jose, California.

5,700 Employees
Last Reported Date: 02/20/14
Founded in 1988

cadence design sys inc (CDS) Top Compensated Officers

Chief Executive Officer, President, Director ...
Total Annual Compensation: $650.0K
Chief Financial Officer, Principal Accounting...
Total Annual Compensation: $400.0K
Executive Vice President of Worldwide Field O...
Total Annual Compensation: $400.0K
Chief of Staff to The Chief Executive Officer...
Total Annual Compensation: $375.0K
Senior Vice President of Research & Developme...
Total Annual Compensation: $350.0K
Compensation as of Fiscal Year 2013.

cadence design sys inc (CDS) Key Developments

Digital Media Professionals, Inc. Selects Cadence Design Systems’s Cadence Palladium XP Platform for Development of its High-Performance Graphic Intellectual Property Cores

Cadence Design Systems Inc. announced that Digital Media Professionals Inc. selected the Cadence® Palladium® XP platform for development of its high-performance graphic intellectual property (IP) cores. The company completed its software stack development before receiving silicon, while also achieving up to 500X simulation performance improvement versus its previous solution. DMP is a provider of 3D/2D graphics and computing IP cores targeting consumer electronics, mobile, embedded and automotive markets. With the Palladium XP platform, and models for peripherals such as DDR3 DFI (DDR PHY Interface) and SD (secure digital) interface, DMP was able to start system emulation early to allow design exploration and pre-silicon system validation with Linux boot and GPU driver optimization.

Cadence Design Systems Inc. Announces the Eleventh Generation of the Tensilica® Xtensa® Processors

Cadence Design Systems Inc. announced the eleventh generation of the Tensilica® Xtensa® processors. The new Xtensa LX6 and Xtensa 11 processors enable users to create innovative custom processor instruction sets with up to 25% less processor logic power consumption and up to 75% better local memory area and power efficiency. The new Xtensa 11 and Xtensa LX6 processors feature several architectural improvements, include enhancements in flexible length instruction extensions (FLIX) for Xtensa LX6 that allow for very long instruction word (VLIW) instructions of any length from 4 to 16 bytes, resulting in code size savings of up to 25% compared to prior Xtensa versions, thus enabling local memory and cache size reductions of up to 25% for the same performance level; an option for run-time power-down of portions of cache memories, yielding up to 75% local memory power savings in select operating scenarios with dynamic cache-way control; more efficient data cache block prefetch lowers system power and boosts system performance by speeding functions such as MemCpy by 6.5 times faster and reducing the total number of system bus read operations by up to 23%; and reduced dynamic switching power of the processor logic gates by up to 25%.

Cadence Design Systems Inc. Announces Fourth Generation Tensilica HiFi DSP Architecture

Cadence Design Systems Inc. announced the Cadence®Tensilica®HiFi 4 audio/voice digital signal processor (DSP) intellectual property (IP) core for system-on-chip (SoC) designs, which offers the performance licensable digital signal processing (DSP) core for 32-bit audio/voice processing. This fourth generation HiFi architecture enables emerging multi-channel object-based audio standards and offers 2X the performance versus the HiFi 3 DSP, making it ideal for DSP intensive applications including digital TV, set-top box (STB), Blu-ray Disc and automotive infotainment. It's key features include support for four 32x32-bit multiplier-accumulators (MACs) per cycle with 72-bit accumulators, more than double the performance of other audio DSPs for computationally intensive functions such as fast Fourier transform (FFT) and finite impulse response (FIR); support for eight 32x16-bit MACs per cycle under specified conditions; Four very long instruction word (VLIW) slot architecture capable of issuing two 64-bit loads per cycle; optional vector floating-point unit available, providing up to four single-precision IEEE floating-point MACs per cycle; software compatible with the existing HiFi DSP family consisting of over 140 HiFi-optimized audio and voice codecs and audio enhancement software packages.

 

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CDS

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Valuation CDS Industry Range
Price/Earnings 41.4x
Price/Sales 3.3x
Price/Book 4.1x
Price/Cash Flow 34.2x
TEV/Sales 2.8x
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