Last €16.37 EUR
Change Today +0.036 / 0.22%
Volume 0.0
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cadence design sys inc (CDS) Snapshot

Open
€16.36
Previous Close
€16.33
Day High
€16.37
Day Low
€16.27
52 Week High
02/26/15 - €16.48
52 Week Low
04/14/14 - €10.41
Market Cap
4.8B
Average Volume 10 Days
0.0
EPS TTM
--
Shares Outstanding
292.3M
EX-Date
--
P/E TM
--
Dividend
--
Dividend Yield
--
Current Stock Chart for CADENCE DESIGN SYS INC (CDS)

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cadence design sys inc (CDS) Details

Cadence Design Systems, Inc. develops, sells, leases, and licenses electronic design automation (EDA) software, emulation and prototyping hardware, verification intellectual property (VIP), and design intellectual property (design IP) for semiconductor and electronics systems industries worldwide. It offers functional verification products, including logic verification software that enables customers to coordinate verification activities across multiple teams and various specialists for verification planning and closure; and system design and verification products for hardware-software verification, as well as for system power exploration, analysis, and optimization. The company also provides digital integrated circuits (ICs) design products, such as logic design products for chip planning, design, verification, and test technologies and services; physical implementation products for use in place and route, signal integrity, optimization, and double patterning preparation; and signoff products to signoff the design as ready for manufacture by a silicon foundry, as well as design for manufacturing products for use in the product development process. In addition, it offers custom IC design and verification products to create schematic and physical representations of circuits down to the transistor level for analog, mixed-signal, custom digital, memory, and RF designs; and system interconnect design products to develop printed circuit boards and IC packages. Further, the company provides design IP products consisting of pre-verified and customizable functional blocks to integrate into customer’s SoCs; and VIP and memory models for use in system-level verification to model correct behavior of full systems interacting with their environments. Additionally, it offers engineering, methodology, education, and hosted design solutions, as well as technical support and maintenance services. The company was founded in 1988 and is headquartered in San Jose, California.

6,100 Employees
Last Reported Date: 02/20/15
Founded in 1988

cadence design sys inc (CDS) Top Compensated Officers

Chief Executive Officer, President, Director ...
Total Annual Compensation: $650.0K
Chief Financial Officer and Senior Vice Presi...
Total Annual Compensation: $400.0K
Executive Vice President of Worldwide Field O...
Total Annual Compensation: $400.0K
Chief of Staff to the Chief Executive Officer...
Total Annual Compensation: $375.0K
Senior Vice President of Research & Developme...
Total Annual Compensation: $350.0K
Compensation as of Fiscal Year 2013.

cadence design sys inc (CDS) Key Developments

Brite Semiconductor Corporation Uses Cadence Design Systems, Inc. Implementation and Signoff Tools

Cadence Design Systems Inc. announced that Brite Semiconductor Corporation, used Cadence® digital implementation and signoff tools to complete four 28nm system-on-chip (SoC) designs and reduced their time to market by three weeks compared to previous design methodologies. By using Cadence tools, Brite Semiconductor was also able to increase performance by up to 20% and reduce power consumption by up to 10% on these designs. Brite Semiconductor adopted the Cadence Encounter® Digital Implementation System for physical implementation and Voltus IC Power Integrity Solution for power signoff and design closure. The Encounter Digital Implementation System, which incorporates GigaOpt route-driven optimization along with CCOpt concurrent clock datapath optimization, helped Brite Semiconductor to improve performance and reduce power consumption. In addition, the Voltus IC Power Integrity Solution enabled Brite Semiconductor to validate, very early on, that the designs functioned as intended, which minimized the risk of design failures later in the process and ultimately reduced development time.

Hitachi Ltd. Utilizes Cadence Design Systems's Virtuoso AMS Designer to Reduces Verification Turnaround Time

Cadence Design Systems Inc. announced that Hitachi Ltd. utilized Cadence Virtuoso AMS Designer to significantly reduce the verification time for a new backplane signal conditioner mixed-signal chip, while also improving quality with chip verification. The rapid growth of mixed-signal design complexity presents considerable verification challenges to reduce time to market and improve design quality. Using Virtuoso AMS Designer together with real number modeling (RNM) techniques, Hitachi was able to simulate the entire design and reduce the verification time from days to minutes. Hitachi presented a paper on this design and their use of Virtuoso AMS Designer and RNM on February 23 at ISSCC 2015 in San Francisco, Calif.

Cadence Design Systems Inc. Announces Stratus High-Level Synthesis Platform

Cadence Design Systems Inc. announced the Cadence® Stratus high-level synthesis platform. This next-generation platform integrates Forte Cynthesizer and Cadence C-to-Silicon Compiler into one tool to deliver 10X productivity improvement, 20% better power, performance, and area (PPA) quality of results (QoR), and 5X faster verification versus a hand-written RTL flow. A sixth generation high-level synthesis core engine to provide excellent usability, scalability, and QoR across the full application space, including both control-centric and datapath-centric designs containing hundreds of blocks. Full integration with Cadence Encounter RTL Compiler and Cadence Encounter® Conformal® ECO Designer to allow physically-aware and ECO-aware high-level synthesis and minimize implementation changes from Engineering Change Orders. Rich intellectual property library of I/O interfaces and customizable floating point datatypes to increase productivity by giving designers synthesizable optimized SystemC building blocks. Full IDE and automation of tool flow and multiple scenario evaluation to enable full architectural exploration, and improve verification by providing a consistent environment from early TLM models through gates.

 

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CDS

Industry Average

Valuation CDS Industry Range
Price/Earnings 35.4x
Price/Sales 3.3x
Price/Book 4.0x
Price/Cash Flow 29.3x
TEV/Sales 2.3x
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