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Last $18.59 USD
Change Today -0.285 / -1.51%
Volume 4.7M
CDNS On Other Exchanges
As of 8:10 PM 05/5/15 All times are local (Market data is delayed by at least 15 minutes).

cadence design sys inc (CDNS) Snapshot

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52 Week High
04/28/15 - $19.83
52 Week Low
05/9/14 - $15.33
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Current Stock Chart for CADENCE DESIGN SYS INC (CDNS)

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cadence design sys inc (CDNS) Details

Cadence Design Systems, Inc. develops, sells, leases, and licenses electronic design automation (EDA) software, emulation and prototyping hardware, verification intellectual property (VIP), and design intellectual property (design IP) for semiconductor and electronics systems industries worldwide. It offers functional verification products, including logic verification software that enables customers to coordinate verification activities across multiple teams and various specialists for verification planning and closure; and system design and verification products for hardware-software verification, as well as for system power exploration, analysis, and optimization. The company also provides digital integrated circuits (ICs) design products, such as logic design products for chip planning, design, verification, and test technologies and services; physical implementation products for use in place and route, signal integrity, optimization, and double patterning preparation; and signoff products to signoff the design as ready for manufacture by a silicon foundry, as well as design for manufacturing products for use in the product development process. In addition, it offers custom IC design and verification products to create schematic and physical representations of circuits down to the transistor level for analog, mixed-signal, custom digital, memory, and RF designs; and system interconnect design products to develop printed circuit boards and IC packages. Further, the company provides design IP products consisting of pre-verified and customizable functional blocks to integrate into customer’s SoCs; and VIP and memory models for use in system-level verification to model correct behavior of full systems interacting with their environments. Additionally, it offers engineering, methodology, education, and hosted design solutions, as well as technical support and maintenance services. The company was founded in 1988 and is headquartered in San Jose, California.

6,100 Employees
Last Reported Date: 02/20/15
Founded in 1988

cadence design sys inc (CDNS) Top Compensated Officers

Chief Executive Officer, President, Director ...
Total Annual Compensation: $650.0K
Chief Financial Officer and Senior Vice Presi...
Total Annual Compensation: $400.0K
Executive Vice President of Worldwide Field O...
Total Annual Compensation: $412.5K
Senior Vice President of Research & Developme...
Total Annual Compensation: $375.0K
Chief of Staff to the Chief Executive Officer...
Total Annual Compensation: $375.0K
Compensation as of Fiscal Year 2014.

cadence design sys inc (CDNS) Key Developments

Cadence Introduces Indago Debug Platform, Improving Debugging Productivity by up to 50%

Cadence Design Systems Inc. announced the Cadence® Indago™ Debug Platform, a new debugging solution which reduces the time to identify bugs in a design by up to 50% compared to traditional signal- or transaction-level debug methods. In addition to the Indago Debug Platform, Cadence also announced three debugging apps that plug into the platform and can be used with other verification tools to provide a single integrated and synchronized debug solution for testbench, verification IP (VIP), and hardware/software debug for system-on-chip (SoC) designs. The Indago Debug Platform and debugging apps are part of the comprehensive Cadence System Development Suite and are currently available for early adopters. General availability is expected by June 2015. With its patented root-cause analysis technology, the Indago Debug Platform filters unneeded data to go beyond the source for a single bug to resolve the cause of all related bugs. Current debug methodologies used by designers require multiple simulation iterations to incrementally extract data points that ultimately point to the source of the bug. The technology in the Indago Debug Platform can reduce the human time necessary to resolve schedule-impacting bugs by up to 50% using a common set of resources that enable a suite of commercial and user-created apps that automate the analysis of data from multiple verification engines and multiple vendors. With a unified debug platform and the debug apps, the Indago Debug Platform enables multiple engineering specialists from design, testbench, embedded software and protocol verification to operate as a team to resolve SoC bugs. The three debug apps are: Indago Debug Analyzer: Extends root-cause analysis from e testbench (IEEE 1647) to SystemVerilog (IEEE 1800) and increases performance by up to 10X. Indago Embedded Software Debug: Resolves bugs associated with embedded software applications by synchronizing software and hardware source code debug. Indago Protocol Debug: Visualizes advanced protocols such as DDR4, ARM® AMBA® AXI and ACE using Cadence VIP for intuitive debugging.

Cadence Design Systems, Inc. Reports Consolidated Unaudited Earnings Results for the First Quarter Ended April 4, 2015; Provides Earnings Guidance for the Second Quarter Ending July 4, 2015 and for the Year Ending January 2, 2016

Cadence Design Systems Inc. reported consolidated unaudited earnings results for the first quarter ended April 4, 2015. For the quarter, the company reported revenue of $411 million compared to revenue of $379 million reported for the same period in 2014. On a GAAP basis, the company recognized net income of $36 million or $0.12 per share on a diluted basis compared to net income of $33 million or $0.11 per share on a diluted basis for the same period in 2014. Using the non-GAAP measure, net income was $72 million or $0.23 per share on a diluted basis as compared to net income of $59 million or $0.20 per share on a diluted basis for the same period in 2014. Net cash provided by operating activities was $46,688,000 against $28,098,000 a year ago. Purchases of property, plant and equipment were $7,520,000 against $6,252,000 a year ago. Income from operations was $49,285,000 against $42,312,000 a year ago. Income before provision for income taxes was $42,312,000 against $38,426,000 a year ago. For the second quarter ending July 4, 2015, the company expects total revenue in the range of $410 million to $420 million. GAAP net income per diluted share is expected to be in the range of $0.14 to $0.16. Net income per diluted share using the non-GAAP measure is expected to be in the range of $0.23 to $0.25. On a GAAP basis, net income is expected to be in the range of $45 to $51 million. On a non-GAAP basis, net income is expected to be in the range of $73 to $79 million. For the year ending January 2, 2016, the company expects total revenue in the range of $1.680 billion to $1.720 billion. On a GAAP basis, net income per diluted share is expected to be in the range of $0.60 to $0.70. Using the non-GAAP measure, net income per diluted share for 2015 is expected to be in the range of $0.96 to $1.06. On a GAAP basis, net income is expected to be in the range of $186 to $218 million. On a non-GAAP basis, net income is expected to be in the range of $300 to $332 million. The company expects operating cash flow to be approximately $350 million and capital expenditure of approximately $40 million.

Cadence Design Systems Inc. to Showcase Latest RF Solutions at International Microwave Symposium 2015

Cadence Design Systems Inc. announced that it plans to showcase its Virtuoso® Custom IC platform, Spectre® RF Simulation solution and Allegro® PCB RFsolution at the International Microwave Symposium, an annual international meeting for technologists involved in all aspects of radio frequency integrated circuits (RFICs) and microwave technology. The event will be held from May 17-22, 2015, in Phoenix, Arizona. RF IC analysis of two Long-Term Evolution (LTE) channels simultaneously using Spectre RF Simulation. Integrating RF PCB circuits quickly, from RF design/analysis tools into mixed-signal PCBs. Testbenches for wireless communication and networking standards such as LTE and Wi-Fi. Advanced S-parameter modeling with broadband SPICE technology. Virtuoso Layout Suite for Electrically Aware Design, featuring real-time layout analysis using built-in parasitic extraction engine that instantly evaluates the layout as it is created.


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Valuation CDNS Industry Range
Price/Earnings 36.0x
Price/Sales 3.3x
Price/Book 4.1x
Price/Cash Flow 29.5x
TEV/Sales 2.4x

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