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Last $20.36 USD
Change Today -0.16 / -0.78%
Volume 1.5M
CDNS On Other Exchanges
Symbol
Exchange
NASDAQ GS
Frankfurt
As of 3:47 PM 09/4/15 All times are local (Market data is delayed by at least 15 minutes).

cadence design sys inc (CDNS) Snapshot

Open
$20.24
Previous Close
$20.52
Day High
$20.51
Day Low
$20.13
52 Week High
08/19/15 - $21.86
52 Week Low
10/16/14 - $15.50
Market Cap
5.9B
Average Volume 10 Days
2.5M
EPS TTM
$0.70
Shares Outstanding
291.4M
EX-Date
--
P/E TM
29.1x
Dividend
--
Dividend Yield
--
Current Stock Chart for CADENCE DESIGN SYS INC (CDNS)

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cadence design sys inc (CDNS) Details

Cadence Design Systems, Inc. develops, sells, leases, and licenses electronic design automation (EDA) software, emulation and prototyping hardware, verification intellectual property (VIP), and design intellectual property (design IP) for semiconductor and electronics systems industries worldwide. It offers functional verification products, including logic verification software that enables customers to coordinate verification activities across multiple teams and various specialists for verification planning and closure; and system design and verification products for hardware-software verification, as well as for system power exploration, analysis, and optimization. The company also provides digital integrated circuits (ICs) design products, such as logic design products for chip planning, design, verification, and test technologies and services; physical implementation products for use in place and route, signal integrity, optimization, and double patterning preparation; and signoff products to signoff the design as ready for manufacture by a silicon foundry, as well as design for manufacturing products for use in the product development process. In addition, it offers custom IC design and verification products to create schematic and physical representations of circuits down to the transistor level for analog, mixed-signal, custom digital, memory, and RF designs; and system interconnect design products to develop printed circuit boards and IC packages. Further, the company provides design IP products consisting of pre-verified and customizable functional blocks to integrate into customer’s SoCs; and VIP and memory models for use in system-level verification to model correct behavior of full systems interacting with their environments. Additionally, it offers engineering, methodology, education, and hosted design solutions, as well as technical support and maintenance services. The company was founded in 1988 and is headquartered in San Jose, California.

6,100 Employees
Last Reported Date: 02/20/15
Founded in 1988

cadence design sys inc (CDNS) Top Compensated Officers

Chief Executive Officer, President, Director ...
Total Annual Compensation: $650.0K
Chief Financial Officer and Senior Vice Presi...
Total Annual Compensation: $400.0K
Executive Vice President and General Manager ...
Total Annual Compensation: $412.5K
Senior Vice President and General Manager of ...
Total Annual Compensation: $375.0K
Chief of Staff to the Chief Executive Officer...
Total Annual Compensation: $375.0K
Compensation as of Fiscal Year 2014.

cadence design sys inc (CDNS) Key Developments

Altair Semiconductor Adopts Cadence Design Systems, Inc.'s Palladium XP Platform for Advanced IoT SoC Development

Cadence Design Systems Inc. announced that Altair Semiconductor adopted the Cadence Palladium XP platform for the verification and validation of its Internet of Things (IoT) system-on-chip (SoC) designs. Using the Palladium XP platform, Altair is able to conduct SoC hardware and software integration and validation three to four months ahead of silicon availability. Altair utilized the Palladium XP platform to accurately model the register-transfer level (RTL) design running with software and flash memory, enabling them to capture half of all hardware and software bugs in a pre-silicon environment. This reduces the development-cycle turnaround time by 20% compared to their previous process. LTE software development for L1, L2 and L3 protocols was completed and verified in the hardware context three to four months before silicon availability.

Cadence Design Systems, Inc. Announces the Cadence® Joules(TM) RTL Power Solution

Cadence Design Systems Inc. announced the Cadence® Joules(TM) RTL Power Solution. This new register-transfer level (RTL) power analysis solution enables system-on-chip (SoC) design teams to analyze power consumption accurately during design exploration. Built on a multi-threaded architecture, the Joules RTL Power Solution delivers 20X faster time-based RTL power analysis when compared to other methods. Incorporating rapid prototype technology from the Cadence Genus(TM) Synthesis Solution engine, the Joules RTL Power Solution can analyze designs of up to 20 million instances overnight with gate-level accuracy within 15% of final power as signed off in the Cadence Voltus(TM) IC Power Integrity Solution. In addition, the Joules RTL Power Solution integrates seamlessly with the Cadence Palladium® emulation platform and the Stratus(TM) High-Level Synthesis (HLS) platform for early system-level power analysis and optimization. Key highlights of the Joules RTL Power Solution include: Accurate RTL power estimation--The Joules RTL Power Solution performs an ultra-fast design synthesis using a new integrated prototype mode of the Genus Synthesis Solution, including physically aware clock tree and datapath buffering, and enabling accurate RTL power estimation. Multi-threaded frame-based architecture--Power analysis is parallelized across multiple CPUs accelerating in-depth power exploration. Multiple stimulus files can be analyzed simultaneously and each stimulus file can be time-sliced into frames to enable time-based power reporting. Adjustable power analysis resolution--User-selectable frames can be used to zoom in on power-critical periods of the simulation, and multiple stimuli for different design hierarchies can be merged to mimic full SoC traffic and power consumption. This enables design teams to easily analyze critical power problems. Advanced data mining and debug--Power can be reported at the bit level or register level and may be categorized based on logic cell type, design hierarchy, clock domain, power domain or timing mode. A rich suite of library analysis and profiling tools is also included. Early system-level power analysis--The Joules RTL Power Solution can be used within the Palladium Dynamic Power Analysis for more accurate time-based power calculations. This provides enhanced production-correlated peak and average power analysis, enabling design teams to analyze system power of software running on hardware early in the development cycle. The Joules RTL Power Solution is also integrated with the Stratus HLS platform for earlier and more accurate power estimates, enabling IP teams to better evaluate system-level micro-architectural tradeoffs.

Realtek Semiconductor Corp Accelerates System-On-Chip Verification with Cadence® Palladium® XP Platform

Cadence Design Systems Inc. announced that Realtek Semiconductor Corp. utilized the Cadence® Palladium® XP platform to accelerate the successful development and verification of a recent system-on-chip (SoC) design. With the Palladium XP platform, Realtek achieved up to 250X faster acceleration versus its previous methodology and was able to improve quality by executing system simulations six months before the silicon was available.

 

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CDNS

Industry Average

Valuation CDNS Industry Range
Price/Earnings 32.4x
Price/Sales 3.5x
Price/Book 4.3x
Price/Cash Flow 26.9x
TEV/Sales 3.0x
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