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Last $18.08 USD
Change Today +0.08 / 0.44%
Volume 2.0M
CDNS On Other Exchanges
Symbol
Exchange
NASDAQ GS
Frankfurt
As of 8:10 PM 03/27/15 All times are local (Market data is delayed by at least 15 minutes).

cadence design sys inc (CDNS) Snapshot

Open
$17.99
Previous Close
$18.00
Day High
$18.11
Day Low
$17.83
52 Week High
12/29/14 - $19.54
52 Week Low
04/22/14 - $13.63
Market Cap
5.3B
Average Volume 10 Days
2.7M
EPS TTM
$0.58
Shares Outstanding
292.6M
EX-Date
--
P/E TM
31.0x
Dividend
--
Dividend Yield
--
Current Stock Chart for CADENCE DESIGN SYS INC (CDNS)

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cadence design sys inc (CDNS) Details

Cadence Design Systems, Inc. develops, sells, leases, and licenses electronic design automation (EDA) software, emulation and prototyping hardware, verification intellectual property (VIP), and design intellectual property (design IP) for semiconductor and electronics systems industries worldwide. It offers functional verification products, including logic verification software that enables customers to coordinate verification activities across multiple teams and various specialists for verification planning and closure; and system design and verification products for hardware-software verification, as well as for system power exploration, analysis, and optimization. The company also provides digital integrated circuits (ICs) design products, such as logic design products for chip planning, design, verification, and test technologies and services; physical implementation products for use in place and route, signal integrity, optimization, and double patterning preparation; and signoff products to signoff the design as ready for manufacture by a silicon foundry, as well as design for manufacturing products for use in the product development process. In addition, it offers custom IC design and verification products to create schematic and physical representations of circuits down to the transistor level for analog, mixed-signal, custom digital, memory, and RF designs; and system interconnect design products to develop printed circuit boards and IC packages. Further, the company provides design IP products consisting of pre-verified and customizable functional blocks to integrate into customer’s SoCs; and VIP and memory models for use in system-level verification to model correct behavior of full systems interacting with their environments. Additionally, it offers engineering, methodology, education, and hosted design solutions, as well as technical support and maintenance services. The company was founded in 1988 and is headquartered in San Jose, California.

6,100 Employees
Last Reported Date: 02/20/15
Founded in 1988

cadence design sys inc (CDNS) Top Compensated Officers

Chief Executive Officer, President, Director ...
Total Annual Compensation: $650.0K
Chief Financial Officer and Senior Vice Presi...
Total Annual Compensation: $400.0K
Executive Vice President of Worldwide Field O...
Total Annual Compensation: $400.0K
Chief of Staff to the Chief Executive Officer...
Total Annual Compensation: $375.0K
Senior Vice President of Research & Developme...
Total Annual Compensation: $350.0K
Compensation as of Fiscal Year 2013.

cadence design sys inc (CDNS) Key Developments

Cadence Design Systems Inc. and ARM Announce Strategic IP Interoperability Agreement

Cadence Design Systems Inc. and ARM announced the signing of a broad Intellectual Property Interoperability Agreement. This multiyear agreement provides reciprocal access to relevant IP portfolios from the Cadence IP Group and ARM. Additionally, the agreement grants both companies rights to manufacture test chips containing Cadence IP and ARM IP and to provide development platforms to customers. The ability to test the IP interoperability in silicon is intended to enable Cadence and ARM to optimize performance and interoperability within systems on chip while accelerating time to market for customers in markets such as mobile, consumer, networking, storage, automotive and the Internet of Things. The IP Interoperability Agreement covers existing and future ARM Cortex processors, ARM Mali GPUs, ARM CoreLink system IP, ARM Artisan physical IP, and ARM POP IP; Cadence Design IP including cores for PCI Express, MIPI, USB, HDMI, DisplayPort, Ethernet, analog, DDR/LPDDR PHY and multiple other memory and storage protocols. This agreement expands upon the successful EDA Technology Access and EDA Subscription Agreements ARM signed with Cadence last year to further enable customers' designs to reach peak performance and power efficiency. Through expanded collaboration, Cadence and ARM are able to develop and deliver solutions that enable customers to rapidly design optimized high-performance ARM-based SoCs and speed time to market for complete systems. This new agreement allows customers of both companies to get to market faster with pre-integrated IP solutions and continue pushing the envelope on low-power and high-performance SoC design.

Spreadtrum Communications Chooses Cadence's Innovus Implementation System

Cadence Design Systems Inc. announced that Spreadtrum Communications (Shanghai) Co. Ltd. has utilized the new Cadence Innovus Implementation System to reduce the turnaround time of a multi-million-cell 28-nanometer (nm) intellectual property (IP) block while delivering to its power, performance, and area (PPA) goals. Spreadtrum's TAT for this IP block was reduced significantly while meeting the original PPA targets compared to its previous solution.

Cadence Design System Introduces Innovus Implementation System

Cadence Design Systems Inc. unveiled Cadence® Innovus™ Implementation System, its next-generation physical implementation solution that enables system-on-chip (SoC) developers to deliver designs with power, performance and area (PPA) while accelerating time to market. Driven by a massively parallel architecture with breakthrough optimization technologies, the Innovus Implementation System provides typically 10 to 20% better PPA and up to 10X full-flow speedup and capacity gain at advanced 16/14/10nm FinFET processes and established process nodes. The Innovus Implementation System was designed with several key capabilities to help physical design engineers achieve best-in-class performance while designing for a set power/area budget or realize maximum power/area savings while optimizing for a set target frequency. The key Innovus capabilities to achieve this include: New GigaPlace solver-based placement technology that is slack-driven and topology-/pin access-/color-aware, enabling optimal pipeline placement, wirelength, utilization and PPA, and providing the best starting point for optimization; Advanced timing- and power-driven optimization that is multi-threaded and layer aware, reducing dynamic and leakage power with optimal performance; Unique concurrent clock and datapath optimization that includes automated hybrid H-tree generation, enhancing cross-corner variability and driving maximum performance with reduced power; Next-generation slack-driven routing with track-aware timing optimization that tackles signal integrity early on and improves post-route correlation; Full-flow multi-objective technology enables concurrent electrical and physical optimization to avoid local optima, resulting in the most globally optimal PPA. The Innovus Implementation System also offers multiple capabilities that boost turnaround time for each place-and-route iteration. Its core algorithms have been enhanced with multi-threading throughout the full flow, providing significant speedup on industry-standard hardware with 8 to 16 CPUs. Additionally, the Innovus Implementation System features the massively distributed parallel solution that enables the implementation of design blocks with 10 million instances or larger. Multi-scenario acceleration throughout the flow improves turnaround time even with an increasing number of multi-mode, multi-corner scenarios.

 

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Industry Analysis

CDNS

Industry Average

Valuation CDNS Industry Range
Price/Earnings 34.9x
Price/Sales 3.2x
Price/Book 4.0x
Price/Cash Flow 28.9x
TEV/Sales 2.3x
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