Semiconductor Manufacturing International Corp., LFoundry Europe GmbH, Marsica Innovation S.p.A - M&A Call
Jun 24 16
To consider purchase of 70% stake of LFoundry for a consideration of EUR 49 million by Semiconductor Manufacturing International Corporation
SMIC and Synopsys Deliver 28-nm HKMG Low-Power Reference Flow
Jun 8 16
Semiconductor Manufacturing International Corporation and Synopsys Inc. announced immediate availability of their joint 28-nanometer (nm) RTL-to-GDSII reference design flow. Developed through deep engineering collaboration between Synopsys and SMIC on the 28-nm High-K Metal Gate (HKMG) process technology, the flow is based on Synopsys' Galaxy Design Platform using key features from the IC Compiler II place and route solution, Design Compiler® Graphical synthesis, StarRC extraction solution, PrimeTime® signoff solution and IC Validator physical verification. Already deployed on hundreds of designs, IC Compiler II addresses today's hypersensitive time-to-market needs by delivering superior quality of results and significant productivity gains with 10X faster design planning, 5X faster implementation and 2X more capacity. ''The reference flow features support for low-power techniques such as power-aware clock tree synthesis, power gating and physical optimization, enabled by industry standard IEEE-1801 UPF (Unified Power Format) power intent. Use of the reference flow allows designers to gain performance, power efficiency and chip density advantages while achieving predictable design closure. The Lynx technology plug-in for the SMIC 28-nm HKMG process extends the reference flow to accelerate design setup and closure with Synopsys' Lynx Design System, a full-chip design environment providing innovative automation and visualization capabilities. This plug-in includes additional process technology information and representative flow and tool settings that help reduce the time it takes to get to optimized design results.
Cadence and Semiconductor Manufacturing International Corporation Collaborate on Delivery of Low-Power 28nm Digital Design Reference Flow
Jun 7 16
Cadence Design Systems Inc. announced a collaboration with Semiconductor Manufacturing International Corporation (SMIC) on the delivery of a 28nm design reference flow that incorporates a full suite of Cadence® digital products for low-power design. This reference flow is a 28nm low-power register-transfer level (RTL) to signoff flow based on the IEEE 1801 low power design and verification standard. It enables system-on-chip (SoC) developers to deliver designs with optimal power consumption, performance and area (PPA), speeding time to market to satisfy ever-increasing computer, consumer electronics, network and wireless product market requirements. The Cadence tools that provide comprehensive support from RTL-to-signoff include: Innovus Implementation System: A next-generation physical implementation tool that incorporates a massively parallel architecture, enabling SoC developers to deliver high-quality designs with highly competitive PPA. The tool also provides key technology for the 28nm process that supports floorplanning, placement and routing with integrated color-/pin-access-/variability-aware timing closure, and clock tree and power optimization; Tempus Timing Signoff Solution: A comprehensive timing analysis tool that significantly reduces signoff timing closure through massively parallel processing and physically aware timing optimization while also delivering silicon-accurate timing and signal integrity analysis to ensure operational chips post-tapeout; Voltus IC Power Integrity Solution: A full-chip, cell-level power signoff tool that provides accurate, fast, and high-capacity analysis and optimization technologies to designers for debugging, verifying, and fixing IC chip power consumption, IR drop, and electromigration (EM) constraints and violations, accelerating IC power signoff and overall design closure; Voltus-Fi Custom Power Integrity Solution: A SPICE-level accurate, transistor-level tool used to analyze and signoff analog, memory and custom digital IP blocks and create accurate macro models that represent the power grid view of the IP blocks during the SoC power signoff run with Voltus IC Power Integrity Solution. It supports comprehensive EM/IR design rules and requirements for the 28nm SMIC process down to the transistor device level; Conformal Low Power Verification: Enables the creation and validation of power intent in context of the design, providing full-chip verification of power-efficient designs; Genus Synthesis Solution: A next-generation RTL synthesis and physical synthesis engine that improves productivity challenges faced by RTL designers, delivering up to 5X faster synthesis turnaround times and scaling linearly beyond 10M instances; Quantus QRC Extraction Solution: A next-generation parasitic extraction tool that is production proven and provides faster runtimes for single and multi-corner extraction and best-in-class accuracy versus the foundry golden reference; Cadence Physical Verification System (PVS): A solution that supports full-chip and in-design signoff. PVS is tightly integrated with the Virtuoso® Custom IC platform, the Innovus Implementation System and the Quantus QRC Extraction Solution to significantly reduce iterations and achieve fastest time to tapeout; Cadence CMP Predictor: Accurately predicts multi-layer thickness and topography variability using a model-based approach developed with a model calibration tool, Cadence CMP Process Optimizer, and identifies potential problem areas (hotspots) that affect yield; Litho Physical Analyzer (LPA): Detects manufacturability issues missed by traditional design rule checks, which helps designers improve yield during physical implementation in a fraction of the time when compared with solutions based on optical proximity correction (OPC) and lithography simulation.