September 21, 2017 5:36 AM ET


Company Overview of Mentor Graphics Corporation

Company Overview

Mentor Graphics Corporation provides electronic design automation software and hardware solutions to design, analyze, and test electro-mechanical systems, electronic hardware, and embedded systems software worldwide. It offers printed circuit boards; Scalable Verification tools; Questa platform to verify systems and integrated circuits (ICs); FastSPICE, Eldo, and ADVance MS analog/mixed signal simulation tools; and Veloce hardware emulation system. The company also provides Calibre DRC and Calibre LVS-H physical verification tools; Calibre xRC and xACT transistor-level extraction and device modeling tools; Calibre resolution enhancement technology tools; Calibre OPCverify tool to check and r...

8005 SW Boeckman Road

Wilsonville, OR 97070

United States

Founded in 1981

5,968 Employees





Key Executives for Mentor Graphics Corporation

Chairman and President
Age: 70
Chief Financial Officer and Director
Age: 50
President of Mentor Graphics Japan and Managing Director of Mentor Graphics Japan
Vice President and General Counsel
Age: 58
Senior Vice President of World Trade
Age: 53
Compensation as of Fiscal Year 2017.

Mentor Graphics Corporation Key Developments

Mentor Graphics Corporation Achieves Certification of the Calibre Physical Verification Platform and Analog FastSPICE Circuit Simulation Platform

Mentor Graphics Corporation announced it has achieved tape-out sign-off certification of the Calibre physical verification platform and Analog FastSPICE circuit simulation platform for the new Intel 22FFL (FinFET low power) process technology. Mutual customers of Intel Custom Foundry and Mentor can now extend their use of Mentor-based flows to perform design rule checking (DRC), layout vs. schematic checking (LVS), electrical reliability analysis, and advanced fill on their integrated circuit (IC) designs for Intel Custom Foundry's new 22FFL design platform. In addition, custom and analog/mixed-signal designers can perform fast, accurate circuit verification and simulation. Intel's 22FFL process is built on Intel's proven FinFET technology backed by years of 22nm/14nm proven manufacturing experience. The new 22FFL offers both high-performance and ultra-low-power transistors with up to 100x lower leakage than Intel's previous 22GP (General Purpose) technology and enables true 22nm class scaling by delivering 17.8 mega transistors per millimeter square. Extensive use of single patterning and simplified design rules make this an affordable, easy-to-use design platform for a broad range of products that is cost-competitive with industry 28 nm processes while providing better performance and power than any planar technology can manage.

Mentor Graphics Corporation extends Solutions for TSMC InFO and CoWoS Design Flows to Help Customers Continue IC Innovations

Mentor Graphics Corporation announced several enhancements to its Calibre® nmPlatform, Analog FastSPICE™ (AFS™) Platform, Xpedition® Package Integrator and Xpedition Package Designer tools in support of TSMC's innovative InFO integrated fan-out advanced packaging and CoWoS® chip-on-wafer-on-substrate packaging technologies. The TSMC InFO and CoWoS 3D packaging technologies enable customers to mix multiple silicon dice on a single device and achieve higher levels of integration and capacity than traditional monolithic ICs. Based on the company Calibre and Xpedition platforms, a full InFO design-to-package verification and analysis suite is now available from Mentor. Key benefits include a fast design-to-tape-out flow based on the Xpedition Package Integrator's rapid hierarchical design prototyping environment, with integrations to the Xpedition Package Designer and the Calibre sign-off verification suite. Additional collaboration extended the cross-probing capability between the Calibre 3DSTACK and Xpedition tools, with the results viewable within the Calibre RVE™ interface. TSMC and Mentor also enabled the Mentor thermal flow (which includes the Mentor AFS and Calibre xACT™ offerings) to support thermal-aware simulation for customers' InFO designs. To enable package-level cross-die timing analysis, Mentor enhanced Xpedition Package Integrator to support a netlisting capability incorporated with Calibre xACT extraction results for InFO and CoWoS designers to verify timing requirements. Reliability is a fundamental component of all design flows. As such, TSMC and Mentor developed stacked-die solutions based on the Mentor Calibre PERC™ reliability platform for both TSMC's InFO and CoWoS flows. This new offering addresses inter-die electrostatic discharge (ESD) analysis.

Mentor Updates to its Embedded Product Portfolio with Broad Coverage for the Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit

Mentor announced an update to its embedded product portfolio with broad coverage for the Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit. This release provides developers with support for the unique combination of multicore processors on the MPSoC development platform with Mentor Embedded Linux, Nucleus RTOS, Mentor Embedded Hypervisor, Code Sourcery tools and Android support. With this release, Mentor Embedded multicore solutions provide the industry's most comprehensive support for the MPSoC to facilitate the development of complex heterogeneous multicore systems. The Xilinx Zynq UltraScale+ MPSoC represents the next generation of multicore platforms for compute-intensive, safety and security systems. Mentor's embedded software and tools portfolio provides MPSoC developers with a one-stop-shop for all their software needs. Mentor Embedded Linux (MEL) is a commercially supported, extensible Linux platform based on the industry standard Yocto Project Running in over 3 billion devices, the Nucleus ® real-time operating system (RTOS) is a proven, highly-scalable real-time operating system designed to meet the most rigorous performance metrics. Both MEL and the Nucleus RTOS can run natively on the MPSoC Cortex-A53 cores in Asymmetric Multi-Processing (AMP) mode, across all Cortex-A53 cores in Symmetric Multi-Processing (SMP) mode, or as a guest OS on Mentor Embedded Hypervisor. The Mentor Embedded Multicore Framework (MEMF) allows developers to configure and deploy multiple operating systems across heterogeneous Zynq UltraScale+ MPSoC processors with or without a hypervisor. The framework supports seamless inter-process communication between MEL, Nucleus RTOS, and bare metal. With the Mentor Embedded Multicore Framework, MEL as the master operating system can boot and shut-down other MEL instances running on Cortex-A53 cores, and Nucleus RTOS or bit manipulation engine (BME)-based applications running on Cortex-A53 or Cortex-R5 cores. The Mentor Embedded Hypervisor (MEHV) is small-footprint, type 1 hypervisor designed to meet the design requirements for open source flexibility, real-time performance, and adherence to industry standards. The framework of MEHV supports Cortex-A53 multicore processor architectures in AMP, SMP or a combination of both. The product portfolio includes Sourcery Codebench to provide a single development environment for all the MPSoC cores and runtimes based on GCC/G++ tools. Sourcery CodeBench with integrated Sourcery Analyzer provides developers with a development environment to create and optimize embedded Xilinx Zynq UltraScale+ Linux, RTOS, hypervisor, and bare metal based applications.

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