Company Overview of Atrenta Inc.
Atrenta Inc. designs and develops system on chip (SoC) realization solutions for semiconductor and consumer electronics industries. It offers SpyGlass that pinpoints structural, coding, and consistency problems in register transfer language (RTL) descriptions; SpyGlass Design for test that enables users to fine tune testability during RTL creation; SpyGlass Power that detects and automatically fixes key power management issues, as well as helps users manage the complexity of multiple power and voltage domains, and verifies power intent defined in UPF; and SpyGlass Constraints that automatically generates new constraints from RTL or netlists based on the topology of the design. The company al...
2077 Gateway Place
San Jose, CA 95110
Founded in 1995
Key Executives for Atrenta Inc.
Chief Executive Officer, President, Founder, and Chairman
Senior Vice President of Engineering
Vice President and Managing Director of India Operations
Vice President of Strategic Development
Compensation as of Fiscal Year 2016.
Atrenta Inc. Key Developments
Atrenta Inc. Presents Expanded RTL Signoff Platform at Design Automation Conference
Jun 4 15
Atrenta Inc. announced that it will present key new additions to its RTL Signoff platform at the 52nd Design Automation Conference to be held June 7-11, 2015 at Moscone Center in San Francisco, California. Atrenta’s RTL Signoff platform, built on its industry SpyGlass, BugScope and GenSys tools, enables efficient verification and optimization of SoCs early in the design cycle, thus minimizing time to design closure and avoiding critical chip failures. While SoCs are becoming bigger and more complex, the use of advanced process nodes has made RTL Signoff a design imperative. At DAC, Atrenta will showcase how its RTL Signoff platform has been expanded to address these challenges. Some key highlights are: SpyGlass Platform: Next generation, SpyGlass Turbo that is Smarter, Faster, and Deeper, IP Signoff solution with a broader industry adoption and hooks for SoC integration, seamless Clock Domain Crossing flow for FPGA designs, static SoC connectivity verification, CDC verification for RTL and netlist including structural, functional and hierarchical methods, reset Domain Crossing verification, timing constraint management including equivalence, propagation and timing exception verification, an integrated platform for RTL power estimation, optimization, and verification and hard-to-test fault analysis at RTL for manufacturing test. GenSys Platform for chip assembly, surgical RTL generation, and SDC restructuring. BugScope Apps for progressive functional /code coverage tracking, and automatic assertion generation for SoC simulation and emulation.
Sibridge Technologies Adopts Atrenta IP Kit
Jun 3 15
Atrenta Inc. announced that Sibridge Technologies has adopted the Atrenta IP Kit into their IP Signoff flow. This addition ensures the most robust and comprehensive analysis of their IP, along with automatic generation of IP quality and specification metrics, resulting in the higher quality and visibility across the critical domains of IP verification. Built on Atrenta’s SpyGlass platform, the IP Kit offers a standardized set of checks, metrics and deliverables for soft (RTL) IP. The IP Kit performs an exhaustive analysis across multiple design disciplines including Simulation & Synthesis readiness, Clock Domain Crossing (CDC), Testability (DFT), Power (estimation, reduction, and verification), Timing Constraints, and Physical congestion. The result of the analysis is a set of objective metrics that report on the quality and readiness of the IP across these domains.
Atrenta Expands SpyGlass for Xilinx FPGAs
Jun 2 15
Atrenta Inc. announced support for the SpyGlass platform working with the Xilinx Vivado Design Suite including support for IEEE 1735 encrypted models and hard macros. With this support, customers will be able to perform comprehensive CDC analysis on RTL designs with embedded Xilinx encrypted IP and hard macros. As FPGA capacity grows, an increasing number of chip designers are targeting System on Chip (SoC) designs on FPGA platforms. To address this growing complexity, FPGA vendors like Xilinx are providing more and more IP blocks for standard functions to maximize design reuse, lower power, and improve efficiency. A significant share of these IP is delivered to customers either encrypted or as hardened macros by Xilinx. Traditionally, 3rd party EDA tools for RTL analysis and verification have treated these as black boxes for lack of visibility into the internals. This approach can be error-prone, especially for CDC verification where it is essential to trace all paths leading into and out of these IP. Atrenta has collaborated with Xilinx to add support for these blocks seamlessly in SpyGlass using IEEE 1735 encryption and also leveraging industry standard models for hard macros. The new integration of SpyGlass and Vivado is available with the Xilinx Tcl Store and enables easy setup and launch of SpyGlass for the end user. This flow leverages both the Xilinx UltraFast Design Methodology and the SpyGlass GuideWare methodology to perform accurate and comprehensive CDC analysis across the entire design, including non-RTL hard macros and IEEE 1735 encrypted RTL blocks.
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