Semiconductors and Semiconductor Equipment
Company Overview of Open-Silicon, Inc.
Open-Silicon, Inc. designs and manufactures semiconductors. The company focuses on SoC realization for traditional ASIC, develop-to-spec, and derivative integrated circuits. It offers SoC architecture, system design, physical design, IP, software, and semiconductor manufacturing services; and OpenMODEL, an ASIC development process. The company was founded in 2003 and is headquartered in Milpitas, California with additional offices in Eau Claire, Wisconsin; Raleigh, North Carolina; North Andover, Massachusetts; Richardson, Texas; and Bengaluru and Pune, India.
490 North McCarthy Boulevard
Milpitas, CA 95035
Founded in 2003
Key Executives for Open-Silicon, Inc.
Senior Vice President of Finance
Director of Engineering Methodology
Compensation as of Fiscal Year 2014.
Open-Silicon, Inc. Key Developments
Open-Silicon Appoints Margie Evashenk to its Board of Directors
Mar 16 15
Open-Silicon announced that Margie Evashenk joins the company's Board of Directors. She joins a company that has grown from being a leader in transforming netlists into ASICs to creating platform-level solutions from customers' market requirement documents. Margie will lend her expertise and market knowledge to help position Open-Silicon to benefit from its full-service, specification-to-volume-production offering.
Open-Silicon Announces Availability of Hybrid Memory Cube 2.0 Memory Controller Intellectual Property
Nov 19 14
Open-Silicon announced a comprehensive Hybrid Memory Cube (HMC) 2.0 controller solution as licensable Intellectual Property (IP) that will enable SoC designers to take immediate advantage of the performance gains afforded by the emerging memory standard. Building upon its experience in working with customers to integrate earlier generations of this critical memory controller interface, Open-Silicon now offers high-quality HMC IP and the sophisticated integration environment required to speed design, reduce cost and ensure product manufacturability. The company is already engaged with a customer to integrate the new HMC 2.0 controller IP into devices for applications such as high-speed networking equipment. HMC is a revolutionary innovation in DRAM memory architecture that sets a new standard for memory performance, power, reliability, and cost. Governed by the Hybrid Memory Cube Consortium (HMCC), the specification fundamentally changes the way memory is built into a system by leveraging 3D packaging to connect multiple DRAM arrays to logic using through silicon vias (TSVs). The HMC 2.0 standard, recently ratified by the HMCC, specifies data rates up to 30 Gb/s. The Open-Silicon HMC 2.0 memory controller IP is a licensable, soft macro implementation that is designed to be compliant with both HMC v1.0 and the upcoming HMC v2.0, supporting all of the defined data rates of both standards. The device seamlessly interfaces to third-party SerDes IP without the need for an additional PCS layer. Moreover, Open-Silicon's recently announced SerDes Technology Center of Excellence (TCoE) will provide ASIC customers a convenient and reliable way to verify and test the integration of the HMC 2.0 memory controller IP with SerDes. Supporting data rates of up to 480 GBytes/s, the IP offers a low latency and a flexible user interface.
Open-Silicon Announces 28Gbps Serializer/Deserializer (SerDes) Evaluation Platform for ASIC Development
Sep 16 14
Open-Silicon announced a 28Gbps Serializer/Deserializer (SerDes) evaluation platform for ASIC development that will enable the rapid deployment of chips and systems for 100G networks. The platform includes a full board with packaged 28nm test chip, software and characterization data. The chip integrates a 28Gbps SerDes quad macro, using physical layer (PHY) IP from Semtech, and meets the compliance needs of the CEI-28G-VSR, CEI-25-LR and CEI-28G-SR specifications. As part of the Open-Silicon SerDes Technology Center of Excellence (TcoE) offering, the 28G SerDes is targeted for ASIC and SoC deployment in high-data-rate, chip-to-chip and chip-to-module applications. Open-Silicon applies its unique, high-speed serial design expertise to ensure the successful delivery of ASICs and SoCs for next-generation, high-speed systems used in the networking, telecom, computing and storage markets. The 28-nm test chip has been packaged in a 19mm x 19mm, 324-ball high performance Low Temperature Co-Fired Ceramic (LTCC) Flipchip substrate. This package material was selected for its relatively wider trace characteristics, low loss tangent, and superior uniform via arrangements that minimize reflections in vertical transitions. Open-Silicon optimized the final package design through simulations to meet and exceed the guidance derived from the CEI specifications. The 28Gbps SerDes evaluation platform will be available by the end of Third Quarter from Open-Silicon.
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