Semiconductors and Semiconductor Equipment
Company Overview of GLOBALFOUNDRIES U.S. Inc.
GLOBALFOUNDRIES U.S. Inc. provides semiconductor manufacturing services for integrated device manufacturer, fabless, and OEM enterprises in the United States and internationally. The company offers integrated circuits, wafers, and microprocessors; and prototyping, mask, and turnkey services. It provides solutions for a range of applications, including mobile communications, consumer electronics, and computer networking. The company was incorporated in 2008 and is headquartered in Santa Clara, California with manufacturing centers in Germany, Singapore, and New York; and regional sales and support offices in Shanghai, Yokohama, Hsinchu, Austin, London, and Munich. GLOBALFOUNDRIES U.S. Inc. op...
2600 Great America Way
Santa Clara, CA 95054
Founded in 2008
Key Executives for GLOBALFOUNDRIES U.S. Inc.
Executive Vice President and Chief Strategy Officer at GLOBALFOUNDRIES
Senior Vice President and General Manager of Singapore Operations
Chief Technology Officer and Senior Vice President
Vice President of Information Technology Solutions
Compensation as of Fiscal Year 2014.
GLOBALFOUNDRIES U.S. Inc. Key Developments
Globalfoundries Appoints Louis Lupin as VP and Chief Legal Officer
Sep 20 14
Globalfoundries reported that Louis Lupin has joined the company as senior vice president and chief legal officer. Lupin has also assumed the role as secretary to the board of directors. Lupin succeeds Alexie Lee, who had served as Globalfoundries' general counsel since the inception of the company and who has recently taken on the role of chief of staff to the CEO. Before joining Globalfoundries, Lupin was a legal consultant to Qualcomm Inc.
GLOBALFOUNDRIES Appoints Sanjay Jha as Chief Executive Officer
Jan 6 14
GLOBALFOUNDRIES announced, from its new offices in Silicon Valley, Sanjay Jha has been appointed as the company's new Chief Executive Officer. Jha has served as CEO of Motorola Mobility Inc. and as the COO of Qualcomm Inc. Ajit Manocha, who served as an advisor to the company's shareholder prior to being appointed CEO of GLOBALFOUNDRIES in mid-2011, will return to that role and will work closely with Jha on his transition. Jha will lead the company's build out and ramp of its Fab 8 leading-edge facility in Malta, New York, supporting customers at the 14 nm technology node. GLOBALFOUNDRIES will also continue its upgrade of facilities in Singapore and Germany, which serve multiple customers across a spectrum of technologies.
Open-Silicon, Inc. and GLOBALFOUNDRIES Demonstrate Custom 28nm SoC Using 2.5D Technology
Nov 21 13
Open-Silicon, Inc. and GLOBALFOUNDRIES announced the demonstration of a functional system-on-chip (SoC) solution featuring two 28nm logic chips, with embedded ARM processors, connected across a 2.5D silicon interposer. The jointly developed design is a proof-of-concept vehicle to showcase the benefits of 2.5D technology for mobile and low-power server applications. At the heart of the custom SoC are two ARM Cortex-A9 processors manufactured using GLOBALFOUNDRIES' 28nm-SLP (Super Low Power) process technology. The processors are attached to a silicon interposer, which is built on a 65nm manufacturing flow with through-silicon-vias (TSVs) to enable high-bandwidth communication between the chips. This approach allows designers to choose the most appropriate process technology for each function of their SoC, while the interposer and TSVs allow for finer grain and lower power connectivity than traditional packaging solutions, leading to smaller form factors and reduced power budgets for next-generation electronic devices. Open-Silicon and GLOBALFOUNDRIES developed the custom SoC to help overcome some of the challenges associated with bringing 2.5D technology to market. The 2.5D system features the following characteristics: logic die including dual-core ARM Cortex-A9 CPUs, as well as DDR3, USB and AXI bridge interfaces, special EDA reference flow designed to address the additional requirements of 2.5D design, including top-level interposer design creation and floor planning, as well as the increased complexity of using TSVs, front-side and back-side bumps, and redistribution layer (RDL) routing, support for additional verification steps brought on by 2.5D design rules, custom die-to-die IO for better area and power characteristics providing a maximum of 8GB/s full-duplex data-rate across the two die through the silicon interposer, development board with memory, boot-ROM, and basic peripherals to demonstrate the die-to-die interface functionality through software running on the CPUs embedded in the logic dies, test methodology consisting of Boundary Scan and Loopback modes, package-related design rules, back-side integration, copper pillar micro-bumping, and 2.5D product assembly by Amkor Technology.
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