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February 10, 2016 6:21 AM ET

Software

Company Overview of Jasper Design Automation, Inc.

Company Overview

Jasper Design Automation, Inc. develops software solutions for semiconductor design, verification, and intellectual property reuse. The company offers JasperGold formal technology platform that validates complex designs, including packet-based data transportation, FIFOs, memories, caches, and multiple clock domains; and Behavioral Indexing technology that enables users to extract, index, and store relevant design behaviors, along with the RTL in a dynamic, executable database. It also offers JasperGold Apps architecture that includes applications for formal property and low power verification, connectivity and X-propagation verification, sequential equivalence checking, architectural modelin...

707 California Street

Mountain View, CA 94041

United States

Founded in 1999

Phone:

650-966-0200

Fax:

650-625-9840

Key Executives for Jasper Design Automation, Inc.

Chief Executive Officer, President and Director
Vice President of Finance
Senior Vice President of Engineering
Chief Architect and Senior Vice President of R&D
Chief Technology Officer
Compensation as of Fiscal Year 2015.

Jasper Design Automation, Inc. Key Developments

Jasper Design Automation Announces Availability of Its New JasperGold(R) Sequential Equivalence Checking App

Jasper Design Automation has announced the availability of its new JasperGold(R) Sequential Equivalence Checking App (SEC App). The new SEC App enables designers to exhaustively verify the sequential functional equivalence of RTL implementations, ensuring that they function identically at sequential design points, -- and 10x faster than competing tools. SOC designers often make changes to RTL that may not be purely functional. Low power optimization, using structures such as clock gating, power gating and power domain partitioning is a common motivation for such changes. Other changes might be motivated by the need to optimize performance or insert ECOs into the design. Faced with two versions of the RTL design, the designer needs to verify that the new RTL is sequentially equivalent to the previous RTL. Moreover, this task must be repeated for every change, however small. Comparing the two versions of the RTL in simulation can take weeks of regression runs. In addition, because simulation is non-exhaustive by nature the results are far from certain. Traditional equivalence checking tools can be used for this task but, so far, the market solutions have been too slow and too limited by the size of the designs that they can handle. The SEC App can accept large sub-system blocks as well as complete SOCs and compare the two versions of the RTL orders of magnitude faster than simulation. The JasperGold SEC App's optimized formal engine executes up to 10x faster than the application of other sequential equivalence checking solutions, and orders of magnitude faster than simulation runs performing a similar task. It also enables the App to handle difficult multi-value logic cases, such as "non-resettable flops," "isunknown," "Verilog 'X' values" and "dangling signals." The SEC App can perform non-cycle accurate verification using temporal and functional mapping. Equipped with this "verification context" technology, it is possible to apply the SEC App to formally compare a high level model or reference model against its RTL implementation. The two models may not necessarily match every cycle, or require certain logical expressions to match.

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