August 24, 2017 1:25 AM ET

Semiconductors and Semiconductor Equipment

Company Overview of Sonics, Inc.

Company Overview

Sonics, Inc. designs, develops, and supplies on-chip network (NoC), security, and power and memory subsystems for semiconductor and system companies globally. It also offers development tools; and power management solutions. The company’s products are used in consumer products, such as smartphones, HDTVs, digital cameras, PSPs, e-books, and other products; Internet-of-Things solutions, including sensors, automotive, and microcontrollers; and cloud infrastructure, such as Wi-Fi, 4G/LTE, CPE/BS/Femto Aps, and routers. Sonics, Inc. was founded in 1996 and is based in Milpitas, California.

670 North McCarthy Boulevard

Suite 100

Milpitas, CA 95035

United States

Founded in 1996

78 Employees

Phone:

408-457-2800

Fax:

408-457-2899

Key Executives for Sonics, Inc.

Co-Founder, Chairman and Chief Executive Officer
Age: 61
Co-Founder, Chief Technical Officer and Director
Senior Vice President of Development Programs
Chief Financial Officer
Age: 57
Vice President of Strategic Programs
Compensation as of Fiscal Year 2017.

Sonics, Inc. Key Developments

ICE-P3 EPU Integrates Temperature-Compensated Voltage And Frequency Control For Maximum Energy Savings

Sonics, Inc. introduced ICE-P3™, the IP industry's first product to automate implementation of dynamic voltage and frequency scaling (DVFS). ICE-P3 is the newest member of the ICE-Grain™ Family of Energy Processing Units (EPU) that identifies, sequences, and controls power state transitions in hardware up to 500X faster than conventional software-based approaches. ICE-P3 includes all of the capabilities and benefits of ICE-G3™-- automated creation of correct by construction EPU hardware and verification environment, rapid scalability to many power grains and derivative designs, MSPS power savings metric, and power control monitoring. It also incorporates several new features that enable power management architects and chip integrators to configure EPUs that automatically control frequency and voltage in their energy-sensitive designs. In chip subsystems with varying throughput requirements, for example CPUs and GPUs, designers using ICE-P3 can minimize average power and total energy by optimizing their circuits to operate at the minimum voltage required to deliver the desired throughput. ICE-P3's autonomous, hardware-based control significantly reduces both dynamic switching and static leakage power components at lower operating voltage. To support voltage and frequency control with temperature and process compensation in ICE-P3, Sonics has extended the "cluster state" concept introduced in ICE-G3™. Now, in addition to power states for each grain in a cluster, an operating point can include up to four independent resource states. Each resource state is mapped to temperature-compensated values for up to four voltage and/or frequency sources. ICE-P3 arbitration circuits enable multiple clusters to safely share the same voltage and/or frequency resources. ICE-P3 also provides voltage and frequency resource controllers that drive the PLL, clock generator, voltage regulator or interface to an external power management IC to request the desired resource value. Sonics has built a customer engagement model for ICE-P3 and the entire family of ICE-Grain EPU products that represents a first for semiconductor IP vendors. The EPU Studio Configuration Trial lets designers test drive the actual IP using the EPU Studio development environment and only requires execution of a simple NDA rather than a full Evaluation License. ICE-P3 is available now.

Sonics, Inc. and Northwest Logic Partner on High Throughput Memory Subsytem Solutions

Sonics, Inc. and Northwest Logic announced their partnership to deliver high throughput memory subsystem solutions for complex System-On-Chip (SOC) designs. The companies' partnership, which is being driven by a mutual customer SOC design win, integrates Sonics' interconnect fabric, SonicsGN® NoC, and Sonics' MemMax® memory scheduler with Northwest Logic's family of HBM2, DDRx, LPDDRx memory controllers.

Sonics, Inc. Introduces ICE-G3

Sonics, Inc. introduced ICE-G3, the second product in the Energy Processing Unit (EPU) family based on the ICE-Grain Power Architecture™. ICE-G3 includes all of the on-chip power management capabilities of ICE-G1™ EPU with the addition of a key new component called the cluster controller. The cluster controller supports definition of complex power states at the system level and implements those system states by closely coordinating the actions of up to 256 lower-level power grain controllers in an EPU design. Sonics has also enhanced its EPU Studio™ development environment to ease definition and automate generation of cluster controllers. As designers partition their system-on-chip (SoC) into a larger number of managed power grains to save energy, they often encounter increasing interdependencies across grains, especially during the sequencing of power state transitions. ICE-G3 cluster controllers enable designers to define cluster operating points with specific power states for each grain controller. The cluster controller maps incoming events into desired operating points, then sequences each grain controller to the specified power state based on user-defined ordering groups that can vary based on operating point. Cluster controller operating points are more powerful than conventional system power states in several ways: 1) they provide hardware protection against illegal operating point transitions, which greatly simplifies power control verification; 2) they support hierarchy, so an SoC-level cluster controller can drive a set of subsystem-level controllers to exploit regularity and enhance reuse; and, 3) they are implemented in fast hardware, ensuring that system power control can leverage the massive MSPS (millions of power states per second) capabilities of EPUs – without losing the ability to change the power control system in software. Sonics has built a customer engagement model for ICE-G3 that represents a first for semiconductor IP vendors. The EPU Studio Configuration Trial lets designers test drive the actual IP using the EPU Studio development environment and only requires execution of a simple NDA rather than a full Evaluation License. The Trial features a fully integrated, step-by-step tutorial to help designers grasp EPU concepts while they rapidly design an EPU for an IoT sensor design in the environment.

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