Semiconductors and Semiconductor Equipment
Company Overview of Sonics, Inc.
Sonics, Inc. designs, develops, commercializes, and supplies on-chip network (NoC) technology solutions for semiconductor and electronics product companies. It offers system IP solutions, which include security, power, and memory subsystems; development tools; performance analysis solutions; and topology structures for the network design. The company also provides SonicsLX (SLX), a NoC that provides systems-on-chip designers with the connectivity needed for CPUs and other processing engines to memory. Its products are used in smartphones, HDTV, digital cameras, PSPs, E-Books, sensors, automotive, microcontrollers, Wi-Fi, 4G/LTE, CPE/BS/Femto APs, routers, and other markets in the United Stat...
670 North McCarthy Boulevard
Milpitas, CA 95035
Founded in 1996
Key Executives for Sonics, Inc.
Chairman, Chief Executive Officer and President
Senior Vice President of Development Programs
Chief Financial Officer and Principal Accounting Officer
Senior Vice President of Operations
Vice President of Marketing
Compensation as of Fiscal Year 2015.
Sonics, Inc. Key Developments
Sonics, Inc. And AlphaChips Collaborate to Develop Advanced SoC Design Platforms
Jul 7 15
Sonics, Inc. announced that it is collaborating with AlphaChips on the development of advanced SoC design platforms. Sonics will provide the SonicsGN NoC for integration of semiconductor IP and consult with AlphaChips on the front-end RTL design flow for the SoC platforms. In addition, Sonics will work closely with AlphaChips on power management specification and implementation for the SoC platforms based on ICE-Grain Power Architecture.
Sonics, Inc. Releases SonicsGN 3.0
Jun 23 15
Sonics, Inc. released SonicsGN ® 3.0, the latest version of the company's NoC. SonicsGN 3.0 expands on the interleaved multi-channel technology (IMT) that has been patented and proven in SonicsSX and includes new layout optimization features for design flows based on modern physical synthesis and place & route tools. SoC architects using SonicsGN 3.0 can eliminate multi-channel DRAM access bottlenecks with IMT and reduce layout tool iterations with flexible user control of hierarchical RTL partitioning and re-timing stage insertion. In SoC designs with multi-channel DRAM subsystems, the processor speed and the total number of processors has grown to the point that the memory bandwidth bottleneck is the biggest problem. The purpose of using multi-channel memory is to exploit parallel access to memory, while avoiding bandwidth loss due to wide DRAM data buses. By breaking data into smaller word sizes and interleaving the transactions across multiple channels, IMT enables designers to improve concurrency and overall throughput by up to 20% using the same external DRAMs. Another related concurrency management problem is ordering of requests that may be simultaneously outstanding to multiple targets, including multi-channel memories. SonicsGN's flexible reordering buffer architecture enables single initiator agents to have transactions outstanding to an arbitrary collection of targets, while respecting the protocol-defined ordering. SoC designers using the reordering buffer can further enhance concurrency by creating separate transaction tags where none existed or by restricting the reordering behavior.
Sonics, Inc. Introduces SonicsStudio 8.0
Jun 8 15
Sonics, Inc. introduced SonicsStudio 8.0, the latest release of its next-generation system-on-chip (SoC) development environment that includes improvements for both designer productivity and power analysis. In Release 8.0, Sonics has added major new features to all three areas of SonicsStudio: the Director user interface, the underlying SonicsStudio generation tools, and the automated development flows for stimulus generation, simulation, synthesis, and performance/power analysis. The focus of Release 8.0 is providing additional information in Director's graphical views that enable designers to see at a glance key characteristics of their network. These improvements to the Director user interface make it much easier to inspect and capture the design. They enable designers to graphically view the clock and power domains and the partitioning. Designers can easily see the width of all the individual links between the NoC routers and agents to quickly perform a visual audit. The re-timing view displays all of the re-timing stages in the different components of the system. If designers are interested in the latency between two components, they can quickly view the entire path and count the number of re-timing stages very directly and intuitively. Release 8.0 provides more design flow automation for performance and power analysis. On the performance analysis side, a new parser imports the results from RTL or third-party ESL simulators into the Director database format with support for complete, multi-hop transaction tracing. This improves analysis and debug performance for designers whether they are using SystemC, RTL or other simulation approaches. SonicsStudio 8.0 is available to early access customers now with general availability in July.
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