Semiconductors and Semiconductor Equipment
Company Overview of Tabula, Inc.
As of March 24, 2015, Tabula, Inc. went out of business. Tabula, Inc. develops programmable semiconductor logic solutions. The company offers 3D programmable logic devices for packet processing applications that enable users to process multiple 100 Gbps packet streams on a single device; 3D tri-gate transistors; Spacetime, a technology that enables a new category of programmable logic devices that reconfigure on the fly at multi-GHz rates executing each portion of a design in an automatically defined sequence of steps; a development board to enable users to evaluate and design with packet processing pre-engineered solutions; NetABAX2 PCIe card for Ethernet and software defined networks to pr...
3250 Olcott Street
Santa Clara, CA 95054
Founded in 2003
Key Executives for Tabula, Inc.
Tabula, Inc. does not have any Key Executives recorded.
Tabula, Inc. Key Developments
Tabula Inc. Announces the DesignInsight(TM) Technology
Oct 1 14
Tabula Inc. announced the DesignInsight(TM) technology, a solution for the design verification and debug of high-performance systems. The result of a multi-year research and development project, this new technology is available today, at no charge to customers, as a part of version 3.0 of Tabula's Stylus(R) software, supporting the ABAX(R) (2) P--Series of 3D programmable logic devices. This breakthrough technology delivers unprecedented levels of device observability and will have a profound effect on the economics and time to market of next-generation communications systems. Tabula delivers the DesignInsight compiler bundled with pre-compiled views as part of their 100G solutions for high-performance packet processing applications. As chip design complexity continues to increase, reducing the development time and subsequent costs associated with verification, validation and debug is a pressing industry challenge. Tabula addresses this complex problem with DesignInsight technology by enabling ABAX(2) customers unprecedented real-time observability into the inner workings of their design, coupled with a seamless verification methodology spanning from RTL simulation to systems deployed in the field. ABAX(2) users can observe signals in a production design operating at full speed (up to 2 GHz) without the need for recompilation or pre-declaration of target signals. Furthermore, there is no need to interrupt the operation of the system in order to change views (collections of signals to be monitored) from one set of signals to another. For Tabula customers, this new technology reduces development costs, accelerates the time to market, increases system uptime/reliability, lowers maintenance costs, and allows for in-depth diagnostics for their end customers. More on DesignInsight Technology: DesignInsight technology consists of three key components, all unique to Tabula: Architecture: The Spacetime(c) 3D programmable architecture, featuring a state element-based interconnect and fine-grained reconfigurability; Silicon implementation: The 22nm ABAX2P1 device, boasting a built-in 2 GHz configuration network, configurable trace buffer, on-the-fly signal reconstruction unit, and programmable trigger unit; Software: Stylus software, enabling the automated reconstruction of signals optimized away in synthesis. All components work in concert to deliver unique capabilities, such as: Any register declared in user RTL can be observed or used as a trigger; Any signal can be observed at full speed -- up to 2 GHz.; No recompilation of the design is required to select signals to observe or to change which signals are observed.; No interruption of the device operations occurs when changing signals or modifying triggers.; New assertions written in SystemVerilog can be created and compiled in minutes and applied to the design transparently during normal device operation, even in systems deployed in the field.; Signals can be viewed as waveforms using industry-standard viewers or downloaded as a spreadsheet in CSV format. The built-in hardware support for the DesignInsight technology in the ABAX2P1 includes: Configurable 1.3 Mb trace buffer; Reconstruction unit enabling on-the-fly reconstructions of all signals including those optimized away during synthesis; Programmable 128-bit trigger unit, enabling implementation of functions such as stateful triggering; USB connectivity. Commands for the DesignInsight compiler are written as a Tcl script or SystemVerilog assertions and compiled into views, which are then loaded in to the device while it is running. As a result, for the first time, designers can extend their use of assertions into hardware, whether in the lab or the field, providing a common design verification and debug methodology throughout the product life cycle. DesignInsight technology is available immediately at no charge, as part of the Stylus 3.0 release and with any of Tabula's development boards. In addition, pre-compiled DesignInsight views are delivered with all of Tabula's 100G pre-engineered solutions, providing users with examples of how this breakthrough technology can provide visibility into key elements of these solutions.
Tabula Inc. and Intel Corporation Work Together To Build a New Multi-100 GigE
Sep 10 14
Tabula Inc. announced that they are working with Intel Corporation to build a new multi-100 GigE line-rate packet processing platform to deliver a flexible, high-performance solution for next-generation data centers. The new solution will feature Intel's silicon photonics technology and Tabula's ABAX2P1 programmable devices and combines long-reach and high-density with the ability to support multiple 100 Gbps flows on a single programmable device. Tabula's multi-100G line-rate packet processing platform will demonstrate a configurable low-latency 4-port 100G L2-L4 switch designed for next-generation routers and data centers. The platform includes two ABAX2P1 programmable devices and offers a flexible combination of 10G, 40G and 100G interfaces in a low-latency, energy-efficient 1U form factor. The platform scales from 112 ports × 10G to 8 ports × 100G and is compatible with both standard 19" rack and Open Rack specifications. Using Intel(R) Silicon Photonics technology, it can transmit multiple high-bandwidth data streams. The platform can be used to develop custom functions such as an embedded switches, TCAM lookup engines or regular expression (RegEx) accelerators operating at 100G line rate. These functions will enable new capabilites for next-generation, purpose-built, top-of-rack (ToR) or leaf switches, aggregation or spine switches, or embedded switches.
Tabula, Inc. Announces Availability of Stylus Compiler Version 2.8.2
Feb 13 14
Tabula, Inc. announced the availability of version 2.8.2 of its Stylus compiler, supporting its ABAX (2) P-Series of devices. Stylus 2.8.2 includes a new 3 x 40G-to-100G low-latency Ethernet bridge reference design, as well as a high-performance search engine soft IP core developed in collaboration with Algo-Logic Systems. These and the many other capabilities included in this release are designed to facilitate next-generation 100G networking equipment development and to further improve user experience. The new capabilities and design kits introduced in the Stylus 2.8.2 release include: A 3 x 40G-to-100G Ethernet bridge: this reference design implements a fully functional 40G Ethernet to 100G Ethernet bridge providing transparent bidirectional bridging between the 40 GigE ports and the 100 GigE port and utilizing deficit-weighted round-robin (DWRR) traffic scheduler for aggregation of the 40 GigE ports. Features include: Three 40G Ethernet ports, One 100G Ethernet port, Forwarding table using Algo-Logic System's EMSE2 soft IP core for 100 GigE traffic, Support of multicast, broadcast and jumbo packets, Host management interface serial port; EMSE2 Hybrid soft IP core: created in collaboration with Algo-Logic Systems, this second generation exact-match search engine (EMSE2) delivers high-performance exact-match search capabilities. The EMSE2 Hybrid core performs up to 150 million searches per second (MSPS), sufficient for a 100G Ethernet traffic stream with minimum-sized 64-byte packets. If additional performance is needed, it is possible to use two or more replicated tables simultaneously. The core supports a wide range of key sizes, including up to 1.5 million entries, and very wide 640-bit keys for even the most demanding applications; DDR3 multi-port front-end reference (MPFE) design: the DDR3 MPFE allows up-to-eight independent (yet synchronous) hosts to drive a single DDR3 hard controller. The MPFE reference design has the following features: Enables up to eight independent ports (operating on the same clock) to drive a single hard DDR3 controller, Supports up to 2133 MT/s ×72 DDR3 throughput, Maintains a user interface that is consistent with the Tabula DDR3 subsystem, enabling easy integration into an existing design; Uses deficit round-robin arbitration to cycle between valid ports to optimize DDR3 efficiency.
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