Synopsys' IC Compiler II to Tape Out 28-nm-FD-SOI SoC
Jun 1 15
Synopsys Inc. announced STMicroelectronics has taped out their latest fully depleted silicon on insulator (FD-SOI) system on chip (SoC) using Synopsys' IC Compiler II place and route solution. Collaborating closely with Synopsys, ST used the tool to complete more than half of the chip, achieving higher designer productivity and better device performance. Unveiled in 2014, IC Compiler II is the successor to IC Compiler, the route solution for advanced design at established and emerging nodes. Driven by the FD-SOI tapeout success, ST is actively engaged in broadening the usage of IC Compiler II. IC Compiler II is a production-ready, full-featured place and route system architected from the ground-up to realize an order-of-magnitude leap forward in designer productivity. It is built on a new multi-threaded infrastructure able to handle designs with more than 500 million instances while continuing to utilize industry-standard input and output formats, as well as familiar interfaces and process technology files.
Synopsys Inc. Expands Virtualizer Development Kit for Renesas RH850 with Support for RH850/P1x Series
May 26 15
Synopsys Inc. expanded its Virtualizer™ Development Kit (VDK) portfolio for Renesas' RH850 MCU with a virtual prototype for the new RH850/P1x series targeting chassis electronic control units (ECUs). The latest virtual prototype builds upon the existing VDK for Renesas RH850 MCUs, which includes support for the F1x, E1x and C1x series MCUs. The Synopsys VDK for Renesas' RH850/P1x is a software development kit that uses a virtual prototype as a target to enable automotive engineers to start software development, integration and test months before physical hardware and testbenches are available, resulting in higher product quality and reduced development cost. The Renesas RH850/P1x virtual prototype was developed through the Center of Excellence collaboration between Renesas and Synopsys, which uses joint engineering teams to develop models and VDKs optimized for Renesas RH850 MCUs. The VDK for Renesas RH850's software debug and analysis tools, combined with support for Synopsys Saber, Mathworks Simulink and Vector CANoe tools enable system integration and testing using a virtual Hardware-in-the-Loop environment. The combined solution accelerates integration and functional safety testing (ISO 26262), resulting in higher ECU and vehicle software quality. Companies can further customize the VDK for RH850/P1x to support all versions of the RH850/P1x or P1x-C MCUs using the Virtualizer tool set and can also call on Synopsys' expert virtual prototyping services to accelerate customization.
Synopsys Announces PCI Express 3.1 IP Solution for Mobile SoCs
May 21 15
Synopsys Inc. announced the lowest power controller and PHY IP solution for PCI Express® (PCIe®) 3.1 specification, significantly reducing both active and standby power consumption for mobile Systems-on-Chips (SoCs). The silicon-proven SynopsysDesignWare® IP for PCIe 3.1 specification incorporates L1 sub-states along with power gating techniques including the utilization of power switches, power islands or retention cells to reduce standby power to less than 10 uW/lane. In addition, supply under drive, a novel transmitter design and equalization bypass schemes cut active power to well below 5 mW/Gb/lane while meeting the PCIe 3.1 electrical specification. By providing a controller and PHY IP solution for PCIe technology that is optimized to deliver the lowest power consumption, Synopsys enables designers to incorporate the necessary functionality into their SoCs and extend the battery life of mobile devices. The DesignWare PHY IP for PCIe 3.1 technology exceeds required PCIe channel performance with multi-phase-locked loops (MPLLs), Feed Forward Equalization (FFE), Continuous Time Linear Equalization (CTLE) and programmable Decision Feedback Equalization (DFE) to enhance signal integrity across high loss and bumpy channels. Separate Refclk Independent SSC (SRIS), reference clock forwarding and PCI Express architecture aggregation and bifurcation provide flexibility and scalability for high-speed SoCs. The PHY's Automatic Test Equipment (ATE) test capabilities, small area and optional wirebond packaging reduce overall bill of materials (BOM) cost. As part of the complete solution, the DesignWare Controller IP for PCI Express 3.1 specification supports L1 sub-states in conjunction with power islands or retention cells for up to 95% lower leakage power during standby mode and very low exit latency, enabling faster wake up time. To reduce active power, the controller supports system-level power management features including Latency Tolerance Reporting (LTR), Optimized Buffer Flush/Fill (OBFF) and Dynamic Power Allocation (DPA). In addition, Synopsys Verification IP (VIP) for the PCIe architecture combined with SystemVerilog source code test suites support the validation of low-power scenarios.
Synopsys Inc. Announces Unaudited Consolidated Earnings Results for the Second Quarter and Six Months Ended April 30, 2015; Provides Earnings Guidance for the Third Quarter and Full Year of 2015
May 20 15
Synopsys Inc. announced unaudited consolidated earnings results for the second quarter and six months ended April 30, 2015. For the quarter, the company reported total revenue of $557,204,000 against $517,697,000 a year ago, reflecting solid organic and acquired company growth. Operating income was $75,927,000 against $63,834,000 a year ago. Income before income taxes was $83,884,000 against $68,059,000 a year ago. Net income was $55,596,000 against $63,317,000 a year ago. Net income per diluted share was $0.35 against $0.40 a year ago. On a non-GAAP basis, net income was $107.6 million, or $0.68 per share, compared to non-GAAP net income of $101.7 million, or $0.65 per share, for the second quarter of fiscal 2014. The company generated $155 million of operating cash flow.
For the six months, the company reported total revenue of $1,099,247,000 against $996,648,000 a year ago. Operating income was $147,426,000 against $123,990,000 a year ago. Income before income taxes was $160,499,000 against $139,243,000 a year ago. Net income was $120,785,000 against $131,013,000 a year ago. Net income per diluted share was $0.77 against $0.83 a year ago. Net cash provided by operating activities was $67,736,000 against $37,911,000 a year ago. Purchases of property and equipment were $43,979,000 against $29,901,000 a year ago. Cash paid for acquisitions and intangible assets, net of cash acquired was $2,303,000 against $367,965,000 a year ago. Capitalization of software development costs was $1,865,000 against $1,875,000 a year ago. On a non-GAAP basis, net income was $233.230 million or $1.48 per share, compared to non-GAAP net income of $194.782 million, or $1.24 per share a year ago.
The company provided earnings guidance for the third quarter and full year of 2015. For the third quarter of 2015, the company expects revenue: $550 million to $560 million, tax rate applied in non-GAAP net income calculations is to be in the range between from 21% to 22%. GAAP earnings per share are to be in the range between from $0.23 to $0.30. Non-GAAP earnings per share are to be in the range between from $0.58 to $0.60.
For the full year 2015, the company expects revenue is to be $2.210 billion to $2.235 billion, a growth rate of approximately 7% to 9%; tax rate applied in non-GAAP net income calculations is to be in the range between from 19% to 20%. GAAP earnings per share are to be in the range between from $1.39 to $1.49. Non-GAAP earnings per share are to be in the range between from $2.76 to $2.81. Cash flow from operations is to be approximately $450 million. Capital expenditures is to be approximately $100 million. The company increasing revenue and non-GAAP EPS guidance, reflecting strong momentum in the first half and its confidence in the rest of the year.
Synopsys Inc. Presents at The Benchmark Company, LLC OneonOne Investor Conference, May-28-2015
May 16 15
Synopsys Inc. Presents at The Benchmark Company, LLC OneonOne Investor Conference, May-28-2015 . Venue: The Pfister Hotel, 424 E. Wisconsin Avenue, Milwaukee, Wisconsin, United States.