synopsys inc (SNPS) Key Developments
Synopsys Inc. Announces the Availability of Version 8.3 of its LightTools® Illumination Design Software
Jul 8 15
Synopsys Inc. announced the availability of version 8.3 of its LightTools® illumination design software, which offers a new Advanced Design Module with robust capabilities for modeling freeform optics for a wide range of applications. The new capabilities enable users to easily incorporate freeform surfaces in illumination designs to produce optical systems that have increased energy efficiency, superior light control and innovative design forms. In addition, LightTools 8.3 delivers new features for highly accurate design and modeling of phosphor-based LED systems. The new LightTools Advanced Design Module introduces a set of specialized tools to enable fast, robust modeling of reflective and refractive freeform optics in both single-surface and segmented configurations for a diverse set of illumination applications. Freeform optical surfaces provide many advantages over conventional optics for meeting complex illumination requirements, such as precise light control, innovative styling, compact system dimensions and energy efficiency. In addition, the Advanced Design Module leverages proprietary algorithms from Synopsys' LucidShape® products that automatically calculate and construct optical geometries based on user-defined illuminance and intensity patterns. This unique, functional approach gives designers the freedom to focus on overall design objectives rather than the implementation details of complex optical components. Key features in the Advanced Design Module include: Freeform Design features for modeling freeform reflective and refractive surfaces that are automatically shaped to form the resulting light pattern. Freeform design features are especially advantageous for systems with small light sources, such as LEDs and halogen lamps. MacroFocal Reflector tool for designing multi-surface segmented reflectors, with different spreads for each facet. MacroFocal Reflector is useful when designing lighting systems for applications that need precise control of the light pattern or sharp intensity cutoffs at one or more sides of the beam. Applications include street lights, outdoor and architectural lighting systems. Procedural Rectangle Lens tool for designing surfaces with pillowed optical arrays, which enable precise light distribution control in LED luminaires and signal lighting, as well as in applications that require superposition of optical distributions. LED Lens tool for creating various types of freeform LED collimator lenses, which are effective for producing efficient, highly directed light distributions. LightTools 8.3 includes new capabilities to assist designers in modeling spatial temperature and power density variations in phosphor-based LEDs. Phosphors are known to change output under various conditions, including wide temperature ranges and changes in power density. These factors are important to consider when modeling phosphor layers in applications such as high-power white LED packages. LightTools 8.3 includes a new application programming interface (API) that gives users a high level of flexibility for developing custom volume scattering components that can be dynamically linked with LightTools. The API is particularly useful for defining interactions in phosphor-based LEDs. A new Volume Scatter Logger has been added to the LightTools Utility Library. The utility creates a log of scattering and phosphor conversion events to show what is happening in a scattering material, such as the amount of absorbed and lost energy, as well as shifts in wavelength. Without this type of capability, designers must infer what is happening within the volume by looking at the exiting rays. The new utility gives users greater insight into where energy density changes occur within the material. LightTools version 8.3 is available now.
Synopsys, Inc. Expands Collaboration with United Microelectronics Corporation
Jul 3 15
Synopsys Inc. and United Microelectronics Corporation, or UMC, have expanded collaboration to include Synopsys DesignWare Embedded Memory IP and the DesignWare STAR Memory System test and repair solution on UMC's second 14-nm FinFET process qualification vehicle, or PQV. The PQV provides additional silicon data, enabling UMC to further tune its 14-nm FinFET process for optimal power, performance and area. This PQV follows the successful tapeout and silicon bring-up of the first UMC 14-nm FinFET PQV containing Synopsys DesignWare Logic Libraries and utilizing the StarRC parasitic extraction tool.
Imagination Selects Synopsys's IC Compiler II Place and Route Solution
Jul 1 15
Synopsys Inc. has announced that Imagination Technologies Group plc has selected Synopsys's IC Compiler II place and route solution as part of the design flow used to tape out its new PowerVR Wizard ray tracing graphics processor test silicon, based on Imagination's reference design. IC Compiler II is a modern place and route system designed and built from the ground up for speed to deliver an overall 10X improvement in designer throughput and productivity. IC Compiler II was built to deliver a major leap forward in physical design throughput and productivity across all process nodes. Its natively architected multi-everything infrastructure and multicore technology enables ultra-high-capacity design planning capabilities and also serves as a scalable foundation for its unique, patented clocking technology and advanced global, analytical design closure techniques which deliver quality-of-results and fastest time to market. With high levels of automation, fast user feedback, incremental and convergent engines, IC Compiler II helps manage the many complexities of design planning and implementation. Through these innovations, IC Compiler II is offering a world of new opportunities by delivering 5X faster runtime along with half the iterations required to achieve the target performance, together proving groundbreaking 10X increase in design throughput.
Synopsys Inc. Unveils 2015.06 Release of IC Compiler II Place and Route Solution
Jun 26 15
Synopsys Inc. has announced the availability of the 2015.06 release of its IC Compiler II place and route solution. The 15.06 release offers cutting-edge capabilities such as the industry's only multi-level design planning for faster closure, advanced total power optimization and innovative context-aware clock tree synthesis techniques for an additional 10% reduction in total power and up to 5% smaller area. With the 2015.06 release of IC Compiler II, Synopsys continues to strengthen its 'power of 10X' solution for widespread deployment across the physical design community. IC Compiler II is Synopsys' next-generation place and route solution designed from the ground up to deliver the high productivity and best QoR for designs across all process nodes. This full-featured, production-ready, netlist-to-GDSII implementation system is built on a brand new multi-threaded infrastructure. It offers ultra-high capacity design planning, unique new clock-building technology and patented global analytical optimization capabilities. These innovative technologies enable IC Compiler II to address today's hypersensitive time-to-market needs by delivering 5X faster runtime along with half the iterations required to achieve target performance, together providing a 10X boost in throughput. The leap forward in productivity realized with IC Compiler II is continuing to deliver transformational benefits to physical designers worldwide. The 2015.06 release of IC Compiler II introduces several advanced technologies to enable additional QoR and throughput advantages for its growing customer base. Innovative capabilities like multi-level design planning enable seamless handling of complex multi- hierarchy design requirements, resulting in faster design closure. Techniques such as total power optimization and context-aware clock tree synthesis deliver smaller area and reduce total power, benefits that are critical to designing at emerging technology nodes. This latest release also includes advanced electro-migration (EM) optimization, native support for mesh and multi-source topologies, and technologies for 10-nm node readiness.
Synopsys Inc. Presents at Nasdaq 32nd Investor Program, Jun-30-2015 08:30 AM
Jun 24 15
Synopsys Inc. Presents at Nasdaq 32nd Investor Program, Jun-30-2015 08:30 AM. Venue: May Fair Hotel, London, United Kingdom. Speakers: Brian M. Beattie, Chief Administrative Officer and Executive Vice President of Business Operations.