synopsys inc (SNPS) Key Developments
Synopsys, Inc. Announces New Extensions to its Open-Source Interconnect Technology Format
Apr 21 15
Synopsys Inc. announced new extensions to its open-source Interconnect Technology Format (ITF) which enable modeling of complex device and interconnect parasitic effects at the advanced 10-nanometer (nm) process node. The new extensions include modeling of variation effects due to multi-patterning technology (MPT). Synopsys collaborated with the members of the Interconnect Modeling Technical Advisory Board (IMTAB), an IEEE-ISTO Federation Member Program, to define and ratify these new extensions. They will be available in the upcoming open-source ITF version 2015.06. MPT is an evolution of the double patterning technology (DPT) first introduced by foundries at the 20-nm process node, and it further extends the use of immersion lithography to 10 nm and below. However, MPT imposes tighter requirements on design implementation and analysis to support layout decomposition into different masks (coloring) and manage increased variation due to misalignment of the multiple masks. Synopsys' advanced MPT solution ratified by IMTAB for 10 nm includes color-aware models that cover all foundry manufacturing techniques including sequential litho-etch patterning, for example, triple patterning (LELELE) and quadruple patterning (LELELELE), as well as spacer-assisted/self-aligned patterning, for example, self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP). In addition to MPT modeling, Synopsys has introduced other ITF extensions approved by IMTAB for more accurate via resistance and device capacitance extraction at advanced FinFET process nodes. At 10nm, via resistivity has increased significantly with growing conductor environment context, so the existing self-aligned via resistance variation model has been extended to include coverage from top and bottom conductors. In addition, new ITF models have been added to accurately extract the floating gate to diffusion contact capacitance for polycide on diffusion edge (PODE) devices and spacer dielectric between gate polycide and contact, both of which are critical to regulating device performance. More information on the new ITF extensions for 10nm can be found in the ITF specifications version 2015.06, targeted for release in June 2015.
Synopsys Inc. to Acquire Software Security Company Codenomicon
Apr 20 15
Synopsys Inc. announced it has signed a definitive agreement to acquire Codenomicon. The additional talent, technology and products will expand Synopsys' presence in the software security market segment and extend the Coverity quality and security platform to help software developers throughout various organizations quickly find and fix security vulnerabilities and protect applications from security attacks. Based in Finland, Codenomicon Oy is well-known and highly respected in the global software security world with a focus on software embedded in chips and devices. Its customer base includes some of the world's leading organizations in telecommunications, finance, manufacturing, software development, healthcare, automotive and government agencies. A team of security engineers at Codenomicon independently discovered the infamous Heartbleed bug while improving a feature in their security testing tools and reported it to the National Cyber Security Centre in Finland. A Codenomicon engineer is credited with naming the bug. Codenomicon's solutions will help Synopsys deliver a more comprehensive security offering for the software development lifecycle by adding its Defensics tool for file and protocol fuzz testing, and its AppCheck tool for software composition analysis and vulnerability assessment. The Codenomicon Defensics tool used to discover the Heartbleed bug automatically tests the target system for unknown vulnerabilities, helping developers find and fix them before a product goes to market. It is a systematic solution to make systems more robust, harden them against cyber-attacks and mitigate the risk of 0-day vulnerabilities. The Defensics tool also helps expose failed cryptographic checks, privacy leaks or authentication bypass weaknesses. The Defensics tool is heavily used by buyers of Internet-enabled products to validate and verify that procured products meet their stringent security and robustness requirements. The Codenomicon AppCheck tool adds software composition analysis capabilities to the Coverity platform, helping customers reduce risks in third-party and open source components. When using the AppCheck tool, customers are able to obtain a software bill of materials for their application portfolios, and identify components with known vulnerabilities. The terms of the deal, which is not material to Synopsys financials, have not been disclosed. The transaction is subject to customary closing conditions and is expected to close within 30 days.
Synopsys, Inc. Announces Immediate Availability of Broad Portfolio of Silicon-Proven IP for TSMC 16-nm FinFET Plus Processes
Apr 8 15
Synopsys Inc. announced the availability of a broad portfolio of DesignWare PHY IP for TSMC's 16-nanometer (nm) FinFET Plus (16FF+) processes, enabling designers to integrate required functionality in mobile and enterprise system-on-chips (SoCs) with less risk. The silicon success of the DesignWare IP in TSMC's 16FF+GL and 16FF+LL processes enables designers to accelerate the development of SoCs that incorporate embedded memories and interface IP for USB 3.0, 2.0 and HSIC; PCI Express 4.0, 3.0 and 2.0; SATA 6G; HDMI 2.0; MIPI D-PHY; DDR4/3 and LPDDR4/3/2 protocols on TSMC 16FF+ processes. The DesignWare STAR Memory System product is a comprehensive, integrated test, repair and diagnostics solution that supports Synopsys and third-party embedded memories. TSMC uses DesignWare STAR Memory System to characterize all of its 16FF+ memory compilers. The optimized test and repair algorithms maximize test coverage while reducing test time, lowering test cost and improving manufacturing yield. Synopsys also provides DesignWare Logic Libraries for the TSMC 16FF+ processes that include 7.5-, 9- and 10.5-track libraries, power optimization kits and High Performance Core (HPC) kits. All Synopsys embedded memories and logic libraries, including those on TSMC 16FF+ processes, work seamlessly with the IC Compiler™ II place-and-route system that accelerates throughput and improves quality of results. The DesignWare USB 3.0 and 2.0, 16G PHY, PCI Express 4.0, 3.0 and 2.0, SATA 6G, HDMI 2.0, MIPI D-PHY, DDR4 multiPHY (including DDR4/3 and LPDDR4/3/2), logic library and embedded memory IP for TSMC's 16FF+ process, as well as STAR Memory System and IC Compiler II, are available now.
Synopsys Inc. Announces the Availability of Version 2.0 of its LucidShape Automotive Lighting Design Software
Mar 31 15
Synopsys Inc. announced the availability of version 2.0 of its LucidShape automotive lighting design software, which delivers a powerful new photorealistic visualization module for efficient performance evaluations early in the design cycle, as well as productivity-enhancing tools to enable faster, more accurate model creation. LucidShape 2.0 empowers automotive lighting engineers to develop, verify and deliver high-quality designs while reducing product development time. LucidShape's new Visualize Module delivers high-speed photorealistic images of an automotive lighting system's lit appearance, which demonstrate luminance effects when light sources in a model are illuminated. Because the Visualize Module depicts all interactions between system geometry and light sources, it provides designers with a physically correct diagnostic tool for evaluating how a lighting system will be perceived by the human eye. This is particularly important for evaluating automotive components such as turn signals and brake lights. The Visualize Module is a fast, reliable engineering tool that enables designers to perform design checks and make improvements early and often in the product development process. The Visualize Module delivers these key capabilities: Supports environment sources for the integration of 360-degree, high-dynamic range (HDR) photographic environments into photorealistic visualizations. Includes all physical and optical properties for an immersive, accurate rendering of a lighting scene. Combines LucidShape's luminance camera and backward ray tracing to perform rapid, high-accuracy luminance calculations and generate photorealistic images at multiple angles and viewing directions. Harnesses LucidShape's GPUtrace solution, which uses graphics processing unit (GPU) computing to accelerate illumination simulations by orders of magnitude compared to multithreading capabilities. The speed of the Visualize Module's simulations gives designers the flexibility to rapidly evaluate their models at any point in the design process.
Synopsys, Inc. Announces Availability of the First Products in New DesignWare EV Family of Vision Processors
Mar 30 15
Synopsys Inc. announced the availability of the first products in the new DesignWare EV Family of vision processors. The EV52 and EV54 vision processors are fully programmable and configurable vision processor IP cores that combine the flexibility of software solutions with the low cost and low power consumption of dedicated hardware. The EV Processors implement a convolutional neural network (CNN) that can operate at more than 1,000 GOPS/W, enabling fast and accurate detection of a wide range of objects such as faces, pedestrians and hand gestures at a fraction of the power consumption of competing vision solutions. To speed application software development, the EV Processor Family is supported by a comprehensive software programming environment based on existing and emerging embedded vision standards including OpenCV and OpenVX, as well as Synopsys' MetaWare Development Toolkit. The combination of high-performance hardware optimized for vision data processing and high productivity programming tools make the EV Processors an ideal solution for a broad range of embedded vision applications including video surveillance, gesture recognition and object detection. The EV Processors include multiple high-performance processing cores that can operate at up to 1 GHz in typical 28-nanometer process technologies. The EV Processors also implement a feed-forward CNN structure that supports a programmable point-to-point streaming interconnect for fast and accurate object detection, a critical task in vision processing. The processors' configurable number of execution units enable developers to exploit the task- and data-level parallelism common in vision applications, executing complex image and video recognition algorithms with as little as one-fifth the power consumption of other vision processors available on the market. A complete software programming environment, including OpenVX and OpenCV libraries, and Synopsys' MetaWare Development Toolkit, simplifies the development of application software for the Synopsys EV Processor Family. The OpenCV source libraries available for EV Processors provide more than 2,500 functions for real-time computer vision. The processors are programmable and can be trained to support any object detection graph. The OpenVX framework includes 43 standard computer vision kernels that have been optimized to run on the EV Processors, such as edge detection, image pyramid creation and optical flow estimation. Users can also define new OpenVX kernels, giving them flexibility for their current vision applications and the ability to address future object detection requirements. The OpenVX runtime distributes tiled kernel execution over the EV Processors' multiple execution units, simplifying the programming of the processor. The full suite of tools and libraries, along with available reference designs, enable designers to efficiently build, debug, profile and optimize their embedded vision systems.