cadence design sys inc (CDNS) Key Developments
Cadence Design Systems Inc. and ARM Announce Strategic IP Interoperability Agreement
Mar 18 15
Cadence Design Systems Inc. and ARM announced the signing of a broad Intellectual Property Interoperability Agreement. This multiyear agreement provides reciprocal access to relevant IP portfolios from the Cadence IP Group and ARM. Additionally, the agreement grants both companies rights to manufacture test chips containing Cadence IP and ARM IP and to provide development platforms to customers. The ability to test the IP interoperability in silicon is intended to enable Cadence and ARM to optimize performance and interoperability within systems on chip while accelerating time to market for customers in markets such as mobile, consumer, networking, storage, automotive and the Internet of Things. The IP Interoperability Agreement covers existing and future ARM Cortex processors, ARM Mali GPUs, ARM CoreLink system IP, ARM Artisan physical IP, and ARM POP IP; Cadence Design IP including cores for PCI Express, MIPI, USB, HDMI, DisplayPort, Ethernet, analog, DDR/LPDDR PHY and multiple other memory and storage protocols. This agreement expands upon the successful EDA Technology Access and EDA Subscription Agreements ARM signed with Cadence last year to further enable customers' designs to reach peak performance and power efficiency. Through expanded collaboration, Cadence and ARM are able to develop and deliver solutions that enable customers to rapidly design optimized high-performance ARM-based SoCs and speed time to market for complete systems. This new agreement allows customers of both companies to get to market faster with pre-integrated IP solutions and continue pushing the envelope on low-power and high-performance SoC design.
Spreadtrum Communications Chooses Cadence's Innovus Implementation System
Mar 11 15
Cadence Design Systems Inc. announced that Spreadtrum Communications (Shanghai) Co. Ltd. has utilized the new Cadence Innovus Implementation System to reduce the turnaround time of a multi-million-cell 28-nanometer (nm) intellectual property (IP) block while delivering to its power, performance, and area (PPA) goals. Spreadtrum's TAT for this IP block was reduced significantly while meeting the original PPA targets compared to its previous solution.
Cadence Design System Introduces Innovus Implementation System
Mar 10 15
Cadence Design Systems Inc. unveiled Cadence® Innovus™ Implementation System, its next-generation physical implementation solution that enables system-on-chip (SoC) developers to deliver designs with power, performance and area (PPA) while accelerating time to market. Driven by a massively parallel architecture with breakthrough optimization technologies, the Innovus Implementation System provides typically 10 to 20% better PPA and up to 10X full-flow speedup and capacity gain at advanced 16/14/10nm FinFET processes and established process nodes. The Innovus Implementation System was designed with several key capabilities to help physical design engineers achieve best-in-class performance while designing for a set power/area budget or realize maximum power/area savings while optimizing for a set target frequency. The key Innovus capabilities to achieve this include: New GigaPlace solver-based placement technology that is slack-driven and topology-/pin access-/color-aware, enabling optimal pipeline placement, wirelength, utilization and PPA, and providing the best starting point for optimization; Advanced timing- and power-driven optimization that is multi-threaded and layer aware, reducing dynamic and leakage power with optimal performance; Unique concurrent clock and datapath optimization that includes automated hybrid H-tree generation, enhancing cross-corner variability and driving maximum performance with reduced power; Next-generation slack-driven routing with track-aware timing optimization that tackles signal integrity early on and improves post-route correlation; Full-flow multi-objective technology enables concurrent electrical and physical optimization to avoid local optima, resulting in the most globally optimal PPA. The Innovus Implementation System also offers multiple capabilities that boost turnaround time for each place-and-route iteration. Its core algorithms have been enhanced with multi-threading throughout the full flow, providing significant speedup on industry-standard hardware with 8 to 16 CPUs. Additionally, the Innovus Implementation System features the massively distributed parallel solution that enables the implementation of design blocks with 10 million instances or larger. Multi-scenario acceleration throughout the flow improves turnaround time even with an increasing number of multi-mode, multi-corner scenarios.
Freescale Speeds SoC Implementation Time by 7X with Cadence Innovus Implementation System
Mar 10 15
Cadence Design Systems Inc. announced that Freescale® Semiconductor has achieved a 7X gain in turnaround time with Cadence® Innovus™ Implementation System over its previous production environment while maintaining its quality of results. The gains were achieved on multiple 3M-instance 28-nanometer (nm) designs for networking applications, which will help the embedded processing solutions company significantly boost engineering productivity and accelerate time to market. Freescale leveraged the Innovus Implementation System full-flow multi-objective technology that enables concurrent electrical and physical optimization, to avoid local optima while achieving excellent quality of results and comparable improvements in power, performance and area (PPA). The Innovus Implementation System is equipped with core algorithms that have been enhanced with pervasive multi-threading throughout the full flow, which provided Freescale with significant speedup on industry-standard hardware with 8 to 16 CPUs.
Juniper Networks Gains Dramatic Throughput and Performance Advantages with Cadence Innovus Implementation System
Mar 10 15
Cadence Design Systems Inc. announced that Juniper Networks has utilized Cadence® Innovus™ Implementation System to improve turnaround time (TAT) for physical implementation of their most complex 28-nanometer (nm) intellectual property (IP) for networking applications. The networking company was able to achieve throughput of more than 1.8 million cells per day while also improving out-of-the-box design performance by 15%. The Innovus Implementation System incorporates the advanced new GigaPlace placement engine and multi-threaded placement optimization, which enabled Juniper Networks to meet its critical performance parameters. The full-flow multi-threading enhancements enabled full utilization of 8- and 16-CPU machines that resulted in the optimal throughput on the multi-million-cell high-performance networking IP blocks.