analog devices inc (ADI) Key Developments
Analog Devices Appoints José Almeida as Board of Director
Jan 21 15
Analog Devices, Inc. announced that Jose (Joe) Almeida has been elected as a Director of the company. Mr. Almeida is currently Chairman of the Board, President and Chief Executive Officer of Covidien.
Analog Devices, Inc. Unveils Direct Conversion Receiver Development Platform for Radar Systems
Dec 10 14
Analog Devices, Inc. announced an integrated direct conversion receiver development platform for radar systems where reduced size, weight and power (SWaP) implementation is critical. The new AD-FMCOMMS6-EBZ platform is a 400-MHz to 4.4-GHz receiver (1350 MHz to 1650 MHz with installed filters) supporting the key L- and S-band frequency radar bands. The platform’s VITA57-compliant form factor ensures seamless connectivity to FMC (FPGA mezzanine card) platforms. The AD-FMCOMMS6-EBZ is suitable for defense, communications, and instrumentation radar systems requiring a high level of integration and performance delivered in a compact footprint. These include early warning detection, weather surveillance, and air traffic control systems. The AD-FMCOMMS6-EBZ receiver platform integrates the AD9652 dual 16-bit A/D converter, ADL5566 high-dynamic-range RF/IF dual differential amplifier, and ADL5380 quadrature demodulator, all of which are COTS (commercial-off-the-shelf) components. A complete design support package is available for the AD-FMCOMMS6-EBZ, and includes schematics, layout files, noise analysis worksheet, FPGA HDL (hardware description language) code, and software drivers. The AD-FMCOMMS6-EBZ utilizes an I/Q demodulator to implement a direct conversion or zero IF architecture in which just one frequency translation is required, compared to a super-heterodyne receiver that must perform several frequency translations. A single frequency translation is advantageous because it reduces receiver complexity and the number of conversion stages needed, which in turn increases performance and reduces power consumption.
F. Grant Saviers Not to Stand for Re-election as Director of Analog Devices, Inc
Dec 5 14
On December 4, 2014, F. Grant Saviers announced the board of directors of Analog Devices, Inc. that he has decided not to stand for re-election at the next annual meeting of the company's stockholders. Mr. Saviers has served as a director of the Company for 17 years. He will continue to serve as a director of the company until his term expires at the company's 2015 annual meeting. Mr. Saviers is a member of the company's nominating and corporate governance committee. Mr. Saviers' decision to not stand for re-election to the board of directors of the company is not due to any disagreement with the company.
Analog Devices, Inc. Presents at Sanford C. Bernstein 2014 Technology Innovation Summit, Dec-17-2014 09:20 AM
Dec 3 14
Analog Devices, Inc. Presents at Sanford C. Bernstein 2014 Technology Innovation Summit, Dec-17-2014 09:20 AM. Venue: Ritz-Carlton, Boston, Massachusetts, United States. Speakers: Vincent T. Roche, Chief Executive Officer, President and Director.
Analog Devices Introduces AD9528 JESD204B Clock and SYSREF Generator
Dec 2 14
Analog Devices, Inc. introduced the AD9528 JESD204B clock and SYSREF generator defined to support the clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs, defense electronics systems, RF test instrumentation, and other emerging wideband RF GSPS data acquisition signal chains. The use of the JESD204B standard for the high-speed converter-to-digital processor interface is becoming increasingly prevalent across many applications as data rates are being pushed into the multi-Gb/s range, and multi-channel synchronization and data latency management are becoming a system necessity. The JESD204B interface was specifically developed to address high-data rate system design needs, and the AD9528 clock device contains functions that support and enhance the unique capabilities of that interface standard. The AD9528 provides a low-power, multi-output, clock distribution function with low-jitter performance, along with an on-chip, two-stage PLL and VCO. The on-chip VCO tunes from 3.6 GHz to 4.0 GHz, with the input receivers and oscillator providing both single-ended and differential operation. The AD9528 provides JESD204B-compatible subclass 1 SYSREF and deterministic latency clocking signals and supports a variety of options for SYSREF signal generation. The most basic is a simple buffer function wherein the user-provided SYSREF signal is fanned out to the SYSREF output pins. When provided with an external SYSREF source, the AD9528 is also capable of synchronizing the SYSREF outputs to the clock outputs being generated internally, which is necessary to achieve accurate deterministic latency. The AD9528 is also capable of generating the SYSREF source internally. The AD9528 supports both continuous signal SYSREF generation and "n-shot" pulse generation. N-shot generation is vital in systems where a continuous signal might result in unwanted spurs in the output spectrum of the data converter being clocked.