A CHIP-DESIGN WIZARD WHO left Toshiba Corp. six years ago has figured out how to cram 6 to 10 times more information into memory-chip cells. The advance could slash the cost of DRAM (dynamic random-access memory) chips by two-thirds or more, says the inventor, Tamio Saito, who is co-founder, president, and CEO of Solidas Corp., based in San Jose, Calif.
Ordinary memory cells store just one bit of data. A high voltage in the memory cell's charge-storing capacitor means the bit is a one; a low voltage means it's a zero. But Saito's so-called ZRAM memory cells are sensitive enough to distinguish tiny differences in voltage--up to 1,000 increments from zero to five volts. Each of those voltage levels stands for a different string of bits--for instance, 0000000000 or 1010101010.
Saito succeeded in using multiple voltage levels by fixing a problem that plagued Toshiba, Hitachi, IBM, and others that have tried multilevel DRAMs--namely, electrical "noise" that distorts the voltage levels. Much of the noise comes from the slamming of the memory cell's transistor gate. So Saito gave each cell a second transistor that works in an opposite way, canceling the noise.
While Saito has achieved 10 bits per cell in the lab, DRAM makers might settle for only six bits per cell in the first generation of mass production. That could be handled with just 64 different voltage levels. Memory access is slightly slower than in a conventional DRAM but fast enough for things such as video buffers and hard-disk controllers. Saito says Solidas is negotiating with five major DRAM makers interested in obtaining manufacturing licenses.