Renesas Achieves 3X Reduction in Chip-Finishing Turnaround Time Using Cadence QuickView Signoff Data Analysis Environment

Renesas Achieves 3X Reduction in Chip-Finishing Turnaround Time Using Cadence                  QuickView Signoff Data Analysis Environment  PR Newswire  SAN JOSE, Calif., July 24, 2014  SAN JOSE, Calif., July 24, 2014 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Renesas Electronics Corporation utilized the Cadence® QuickView Signoff Data Analysis Environment to achieve a 3X improvement in chip-finishing turnaround time over its previous solution. As a result of this productivity gain, Renesas has standardized on the Cadence® QuickView Signoff Data Analysis Environment to maximize tapeout productivity for all technology nodes.  Cadence Logo.  The QuickView Signoff Data Analysis Environment is a high-performance, high-capacity data-analysis tool that enables viewing and superimposing of design data in any of its intermediate conditions throughout the chip-finishing process. The QuickView Signoff Data Analysis Environment is also compatible with third-party IC implementation flows and can read file formats used by third-party verification tools. The solution's comprehensive database operations—intelligent overlay, graphical XOR capabilities, synchronized multi-windows, net tracing, LEF/DEF support, merging/converting data, and cross-section views—make graphical comparisons of data easy by providing an additional element of decision support to tapeout engineers.  "After full-chip verification, opening the database for chip finishing can take hours, and because there are several iterations at this stage, any productivity loss has a large impact on time-sensitive project schedules and deadlines," said Tatsuji Kagatani, department manager, Design Automation Department System Integration Business Division, Renesas Electronics Corporation. "We selected the QuickView Signoff Data Analysis Environment after a stringent evaluation, wherein Cadence delivered the best performance and capabilities. This enabled our design teams to improve their productivity and reduce iterations at tapeout."  For more information on the QuickView Signoff Data-Analysis Environment, visit www.cadence.com/news/quickview.  About Cadence  Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.  © 2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.  For more information, please contact: Cadence Newsroom 408-944-7039 newsroom@cadence.com  Logo - http://photos.prnewswire.com/prnh/20140102/SF39436LOGO  SOURCE Cadence Design Systems, Inc.  Website: http://www.cadence.com  
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