Elbit Systems Deploys Aldec DO-254/CTS and Passes EASA Verification Audit for Level A System

  Elbit Systems Deploys Aldec DO-254/CTS and Passes EASA Verification Audit
  for Level A System

Business Wire

HENDERSON, Nev. -- June 16, 2014

Aldec, Inc. announces that Elbit Systems, Ltd. has successfully passed a
critical verification audit by the European Aviation Safety Agency (EASA) with
Aldec’s DO-254/CTS™ as the primary FPGA physical testing platform.

Elbit’s project consisted of multiple FPGAs from different types in which each
FPGA consisted of multiple clock domains and high speed interfaces to PCI,
ARINC and LVDS. Elbit verified FPGA pin-level requirements using DO-254/CTS
custom boards and verified board level requirements using their target board.
By deploying Aldec’s DO-254/CTS in their verification flow, Elbit increased
functional verification coverage by test and reduced the overall verification
cycle. EASA supported Elbit’s FPGA testing approach facilitated by Aldec’s
DO-254/CTS.

“EASA approved our verification process based on Aldec DO-254/CTS, accepted
our test results and the audit passed without any findings,” said Moshe
Porian, Logic Design Verification Group Leader at Elbit Systems Aerospace
Division. “This is the first time in Elbit’s history that we have been able to
bring more than five FPGA devices to the audit. Aldec helped us solve several
of our verification challenges, and delivered quick and professional responses
for all our requests.”

“FPGA requirements-based testing is critical to DO-254 compliance, but in most
cases not feasible to do in the target board due to the lack of FPGA input
control and output access points - this created major challenges for Elbit,”
said Louie De Luna, DO-254 Program Manager at Aldec. “DO-254/CTS solved
Elbit’s major challenges and they were able to test in hardware 100% of FPGA
pin-level requirements. As opposed to developing software test vectors, Elbit
used their simulation testbench as test vectors for FPGA at-speed testing
which cut their development costs.”

“Elbit needed to implement robustness testing for their design assurance level
(DAL) A FPGAs. By executing the simulation environment in hardware using
DO-254/CTS boards, Elbit was able to catch bugs which gave them verification
credits for robustness,” said Zibi Zalewski, General Manager of Aldec’s
Hardware Products Division. “Additionally, we also provided testing
capabilities for abnormal operating conditions with input voltage and clock
frequency variations that are all fully scriptable. This enabled automated
testing of all FPGA requirements after each change of code, including advanced
results comparison functions.”

About DO-254/CTS™

DO-254/CTS is a fully customized hardware and software platform that augments
target board testing to increase verification coverage by test and satisfy the
verification objectives of DO-254/ED-80. The target design runs at-speed in
the target device mounted on the custom daughter board. The simulation
testbench is used as test vectors to enable requirements-based testing with
100% FPGA pin-level controllability and visibility necessary to implement
normal range and abnormal range tests. The FPGA testing results are captured
at-speed and displayed using a simulator waveform viewer for advanced analysis
and documentation. For more information, go to www.aldec.com/do254.

About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is a 30-year industry leader
in Electronic Design Verification and offers a patented technology suite
including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design
Rule Checking, IP Cores, Requirements Management, DO-254 Functional
Verification and Military/Aerospace solutions. www.aldec.com

Aldec is a registered trademark of Aldec, Inc. All other trademarks or
registered trademarks are property of their respective owners.

Contact:

Aldec, Inc.
Christina Toole, +1-702-990-4400
christinat@aldec.com
 
Press spacebar to pause and continue. Press esc to stop.