MoSys Announces Tabula Support of GigaChip Interface
GigaChip Interface Enables Unparalleled Memory Capabilities in 100G and Beyond
SANTA CLARA, Calif. -- November 21, 2013
MoSys (NASDAQ: MOSY), a leader in semiconductor solutions that enable fast,
intelligent data access for network and communications systems, today
announced that Tabula, Inc., advancing high-performance programmable logic
solutions for network infrastructure systems, supports the GigaChip™
As networking equipment transitions from 10G to 40G to 100G and beyond,
greater access to memory is increasingly required to execute complex packet
header processing operations for line rate switching, routing, monitoring and
security. Programmable logic devices from Tabula offer substantial on-chip
bandwidth and off-chip memory capacity using commodity external memory.
However, traditional memory solutions lack sufficient access to memory,
exposing a bottleneck which strangles the overall system performance. Using
MoSys® Bandwidth Engine® serial memory solutions combined with the highly
efficient GigaChip Interface alleviates this chokepoint in the system by
providing four times the access performance of traditional memory solutions.
“Increased performance and bandwidth in the system are critical in order to
meet the requirements for cutting-edge networking equipment. But, if the
packet processors cannot access memory at the rates required, then the overall
system performance suffers,” stated John Monson, VP of Marketing for MoSys.
“Memory access bottlenecks disappear, however, when standard operations are
offloaded to MoSys’ Bandwidth Engine through our ninety-percent efficient
GigaChip Interface. We are pleased that Tabula has selected the GigaChip
Interface as a key design feature, enabling Tabula devices to deliver
next–generation packet processing performance.”
MoSys’ Bandwidth Engine solution provides high-access rates to high-speed
memory using the GigaChip Interface and can accelerate performance by more
than 4 times through intelligent offload of counters, metering functions,
semaphores and transactional memory operations for link-list management. These
types of intelligent offload capabilities enable high-bandwidth,
high-efficiency chip-to-chip communications necessary for high-performance
switching, routing, monitoring and content processing functions.
"As a leading provider of breakthrough programmable logic solutions for
today’s most challenging 100G systems applications, Tabula is always looking
for partnerships that offer our customers innovative, powerful solutions,”
said Alain Bismuth, Vice President of Marketing for Tabula. “Through our
support of MoSys' GigaChip Interface and Bandwidth Engine devices, we can
deliver overall memory capabilities not achievable with competing solutions.”
The GigaChip Interface (GCI) is a scalable, high-performance, serial protocol
for chip-to-chip communications that is differentiated in efficiency and
reliability, resulting in system level benefits of reduced power, cost and
complexity. Current implementations built with compatible CEI-11G or XFI
SerDes electrical transport standards deliver up to 144Gbps of full duplex
data throughput using 16 SerDes lanes when running at a 10G rate. A key
differentiator for the GCI protocol is high transport efficiency, even for
small payloads. Alternative serial interfaces are typically less than 50
percent efficient when transferring 8B and 16B data, which means that they
deliver less than half the performance at a given bandwidth. The combination
of 90 percent transport efficiency, from small to large payloads, combined
with power-efficient short-reach physical interconnect makes GCI ideal for
co-processor, memory or multi-chip communication. The interface also includes
CRC error detection and automatic error recovery provisions to meet the high
reliability requirements of enterprise, service provider and mission-critical
communications and compute applications. GCI is an open, royalty-free,
interface specification designed for use with the MoSys Bandwidth Engine
family of ICs and is suitable for any chip-to-chip interconnect.
MoSys also announced, in accordance with NASDAQ Listing Rule 5635(c)(4), as a
material inducement to the hiring of four new employees, it has granted or
offered to grant stock options for a total of 158,000 shares of common stock.
Inducement option grants have an exercise price equal to the closing price of
MoSys' common stock on the NASDAQ market on the grant date, and vest over four
years and expire in ten years, assuming continued service.
About MoSys, Inc.
MoSys, Inc.(NASDAQ: MOSY) is a fabless semiconductor company enabling
leadingequipment manufacturers in the networking and communications
systemsmarketstoaddress the continual increase in Internet users, data and
services.The company'ssolutions deliver data path connectivity, speed and
intelligence while eliminating data access bottlenecks on line cards and
systems scaling from 100G to multi-terabits per second. Engineered and built
for high-reliability carrier and enterprise applications, MoSys' Bandwidth
Engine® and LineSpeed™ IC product families are based on the company's patented
high-performance, high-density intelligent access and high-speed serial
interface technology, and utilize the company's highly efficient GigaChip™
Interface.MoSysis headquartered inSanta Clara, California. More information
is available atwww.mosys.com.
Bandwidth Engine, the GigaChip logo andMoSysare registered trademarks
ofMoSys, Inc.in the US and/or other countries. GigaChip, LineSpeed and
theMoSyslogo are trademarks ofMoSys, Inc.All other marks mentioned herein
are the property of their respective owners.
Kristine Perham, +1-408-418-7670
Beverly Twing, +1-972-239-5119 ext. 126
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