Cadence Introduces Voltus IC Power Integrity Solution, Delivering Exceptional Performance and Capacity in Power Signoff

Cadence Introduces Voltus IC Power Integrity Solution, Delivering Exceptional 
Performance and Capacity in Power Signoff 
SAN JOSE, CA -- (Marketwired) -- 11/12/13 --  Cadence Design Systems,

--  New power integrity analysis engine with massively parallel execution
    brings up to 10X faster performance
--  New hierarchical architecture supports very large designs up to 1
    billion instances
--  Tightly integrated with key Cadence tools throughout the design flow,
    including Cadence Tempus Timing Signoff Solution, for the fastest
    design closure in the industry

Addressing the critical power challenges faced by electronics
developers, Cadence Design Systems, Inc. (NASDAQ: CDNS) today
introduced Voltus(TM) IC Power Integrity Solution, delivering record
performance and capacity power analysis to meet the needs of
next-generation chip design. Voltus IC Power Integrity Solution draws
on unique new technology as well as integration with Cadence(R) IC,
package, PCB and system tools to enable design teams to better manage
power issues throughout the product development cycle and achieve
faster design closure. 
"As a global leader in embedded processing semiconductor solutions,
Freescale is always on the lookout for new design tools that help us
innovate and create at the most advanced levels of technology," said
Ken Hansen, vice president and chief technology officer at Freescale
Semiconductor. "We are teaming early on with Cadence to validate the
Voltus technology and we are impressed by its performance gains. This
type of enhanced productivity is invaluable to help us meet our
time-to-market goals." 
Following the May release of Tempus(TM) Timing Signoff Solution, the
Voltus solution marks the second major new product this year from
Cadence aimed at speeding design signoff and closure. Using the
Voltus solution, Cadence customers can shrink the critical power
signoff closure and analysis phase to a minimum through key
capabilities including: 

--  A new massively distributed parallel power integrity analysis engine
    that delivers a scalable performance gain up to 10X over competing
--  A hierarchical architecture that, coupled with the parallel execution,
    scales to multiple CPU cores and servers, enabling the analysis of
    designs of up to a billion instances
--  SPICE-accurate solver technology that provides the most accurate power
    signoff results
--  Physically-aware power integrity optimization, such as early rail
    analysis, de-coupling cap and power gating switches, that improves
    physical implementation quality and speeds up design closure
--  Voltus IC Power Integrity Solution delivers these capabilities as a
    standalone product, but provides even greater benefits when integrated
    with other Cadence tools:
--  The industry's first unified electrical signoff solution for faster,
    converged timing and power signoff, when used with Tempus Timing
    Signoff Solution
--  A unique and comprehensive power integrity solution encompassing chip,
    package and PCB when combined with Encounter(R) Digital
    Implementation System and Allegro(R) Sigrity(TM) Power Integrity
--  Analysis of custom/analog IP in an analog mixed-signal SoC design when
    integrated with Virtuoso(R) Power System
--  Accurate IC chip power integrity analysis, driven by real-world power
    stimulus when used with Palladium(R) Dynamic Power Analysis

"With power issues playing an ever-growing role in SoCs, we realized
that existing technology would not meet the needs for complex
designs," said Anirudh Devgan, Senior Vice President of the Digital
and Signoff Group (DSG) at Cadence. "Voltus IC Power Integrity
Solution is Cadence's answer to these challenges, and all our early
adopters are reporting great successes on its performance and
capacity, including on-time tapeout for one of the industry's largest
 Voltus IC Power Integrity Solution is available
now. Cadence will showcase the Voltus capabilities at the Signoff
Summit on Nov. 21 at Cadence headquarters in San Jose, Calif. For
more information about the Signoff Summit, please click here. For
more information about Voltus IC Power Integrity Solution, visit the
Cadence website at  
About Cadence
 Cadence enables global electronic design innovation
and plays an essential role in the creation of today's integrated
circuits and electronics. Customers use Cadence software, hardware,
IP, and services to design and verify advanced semiconductors,
consumer electronics, networking and telecommunications equipment,
and computer systems. The company is headquartered in San Jose,
Calif., with sales offices, design centers, and research facilities
around the world to serve the global electronics industry. More
information about the company, its products, and services is
available at  
Copyright 2013 Cadence Design Systems, Inc. All rights reserved
worldwide. Cadence, Encounter, Allegro, Virtuoso and the Cadence logo
are registered trademarks of Cadence Design Systems, Inc. in the
United States and other countries. All other trademarks are the
property of their respective owners. 
For more information, please contact:
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