Altera Quartus II Software v13.1 Delivers Up to 70 Percent Reduction in
Release Includes Compile Time Advancements and Enhanced High-Level Design
Flows to Increase Productivity
SAN JOSE, Calif., Nov. 5, 2013
SAN JOSE, Calif., Nov. 5, 2013 /PRNewswire/ --Altera Corporation (NASDAQ:
ALTR) today announced the release of its Quartus® II software version 13.1,
extending its industry leadership in software productivity by delivering on
average 30 percent and up to 70 percent reduction in compile times compared to
the previous version, through significant algorithm optimization and increased
parallelization. The software also includes the newly available Rapid
Recompile feature for customers making small source code changes on Altera
Stratix® V FPGA designs. With Rapid Recompile, customers can reuse previous
compilation results to preserve performance, without the need for up-front
design partitioning, and achieve an additional 50 percent compile time
"Our Quartus II software has been able to evolve with each generation of FPGA
products because of our superior and proven software architecture that was
designed right the first time," said Alex Grbic, director, software and IP
product marketing. "With new capabilities and enhancements to the latest
version of the Quartus II software, we are delivering a 2X compile time
advantage and a 20 percent performance advantage over the competition with our
This latest version extends the Quartus II software's leadership by also
delivering enhancements to high-level design tools, so customers can maximize
productivity and benefit from the leading-edge capabilities of Altera devices.
Quartus II software version 13.1 delivers enhancements to its Qsys system
integration tool, DSP Builder model based design environment and the Altera
SDK for OpenCL™.
oAltera Qsys system integration tool saves significant time and effort
throughout the FPGA design cycle by automatically connecting together
intellectual property (IP) functions and subsystems. Using Qsys, designers
can seamlessly integrate a mix of industry-standard interfaces, including
Avalon, ARM® AMBA AXI, APB and AHB interfaces, for faster system
development. In Quartus II software v13.1, Qsys further improves
productivity with enhanced system visualization, allowing multiple
simultaneous views of the Qsys system. This makes modifying the system,
either by adding or connecting components to new a peripheral, much
oAltera SDK for OpenCL is now in full production and is the industry's only
FPGA OpenCL solution to pass conformance testing by adhering to the OpenCL
specification defined by the Khronos Group. It provides a
software-friendly programming environment to design high-performance
systems that use FPGAs on Altera's Preferred Board Partner Program boards
or Altera SoCs when using the Altera Cyclone® V SoC development board.
oAltera DSP Builder Design Tool enables system developers to effectively
implement high-performance, fixed- and floating-point algorithms into
their digital signal processing (DSP) designs. To give engineers more
options and flexibility during the design phase, Altera DSP Builder
Advanced Blockset systems can now be integrated within MathWorks HDL
Coder. Improvements in fast Fourier transform (FFT) processing include
variable-sizing of FFTs at run-time and super-sampling FFTs for extremely
high data rates of 10GHz, giving unprecedented performance and flexibility
options to those implementing this common DSP function.
Quartus II software version 13.1 includes Altera's best-in-class IP, offering
up to 70 percent lower latency and more than 50 percent resource utilization
reduction while maintaining customer's performance and throughput of the most
heavily used and highest performance IP. These IP cores cover 10G, 40G and
100G Ethernet, and 25G to 150G Interlaken.
For additional information about the features offered in Quartus II software
v13.1, visit Altera's What's New in Quartus II Software web page.
Pricing and Availability
Both the Subscription Edition and the free Web Edition of Quartus II software
v13.1 are now available for download. Altera's software subscription program
makes it easy to obtain Altera design software by consolidating software
products and maintenance charges into one annual subscription payment.
Subscribers receive Quartus II software, the ModelSim®-Altera Starter edition,
and a full license to the IP Base Suite, which includes Altera's most popular
IP (DSP and memory) cores. The annual software subscription is $2,995 for a
node-locked PC license and is available for purchase at Altera's eStore.
The annual software subscription for the Altera SDK for OpenCL is $995 for a
node-locked PC license. For additional information about the Altera Preferred
Board Partner Program for OpenCL and its partner members, or to see a list of
all supported boards and links to purchase, visit the OpenCL section on
Altera® programmable solutions enable designers of electronic systems to
rapidly and cost effectively innovate, differentiate and win in their markets.
Altera offers FPGAs, SoCs, CPLDs, ASICs and complementary technologies, such
as power management, to provide high-value solutions to customers worldwide.
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SOURCE Altera Corporation
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