Lattice Semiconductor Selects Silicon Frontline for Electrostatic Discharge (ESD) Analysis

Lattice Semiconductor Selects Silicon Frontline for Electrostatic Discharge 
(ESD) Analysis 
CAMPBELL, CA -- (Marketwired) -- 09/05/13 --  Silicon Frontline
Technology, Inc. (SFT) an Electronic Design Automation (EDA) company
in the post-layout verification market, announced today that Lattice
Semiconductor, Inc. (NASDAQ: LSCC), the provider of innovative FPGA
and PLD semiconductor solutions, picked Silicon Frontline's ESRA
(ElectroStatic discharge Reliability Analysis) software for fast,
full-chip ESD (ElectroStatic Discharge) analysis. ESRA improves the
reliability and quality of semiconductors offered by Lattice. 
"Lattice is focused on providing customers with the industry's
lowest-power, lowest-density, lowest-cost programmable logic devices
and full-chip ESD design validation is a critical part of protecting
the integrity of our products," stated Choon-Hoe Yeoh, Senior
Director EDA Tools and Methodologies at Lattice. "After extensive
evaluations of various options, we selected Silicon Frontline's ESRA
software as our standard full-chip ESD sign-off solution for all our
FPGA and CPLD designs because it meets our capacity, accuracy,
ease-of-use and cost requirements." 
"We are proud to have Lattice Semiconductor select our ESD software
to verify and improve the quality of their devices," said Yuri
Feinberg, SFT CEO. "Because of today's requirements to support
multiple power domains, the demands on designers, with respect to ESD
analysis, continue to escalate. ESD events are responsible for over
25% of silicon failures. Verifying nanometer designs with multiple
power domains before silicon test, with our software, can avoid
re-designs and re-spins, leading to better quality silicon and
satisfied customers."  
ESRA provides a full-chip ESD analysis solution. It delivers
extraction, simulation, analysis, and debugging capability in one
integrated environment. Highlighted resistance and current density
violations permit designers to perform layout corrections at any time
in the design process. 
Why ESD Analysis Is Important 
 Today's advanced process technologies
create reliability challenges for IC designers. Thinner gate oxides
and narrower wires, coupled with multiple power domains,
significantly increase the threat of ESD failures. ESD failures are
mos
t often only identified in silicon testing, leading to re-designs
and re-spins. 
Silicon Frontline's Products 
 ESRA offers designers comprehensive
verification and optimization strategies to improve ESD protection.
It allows designers to verify the full chip for ESD reliability;
pinpoint areas susceptible to failure; work on pre- and post-LVS
(Layout Versus Schematic) clean designs; handle CDM (Charged Device
Model), MM (Machine Model) and HBM (Human Body Model) ESD events; and
optimize ESD device area. F3D (Fast 3D) is used for fast 3D
extraction, and R3D (Resistive 3D) is used for 3D extraction and
analysis of large resistive structures. F3D are chosen for their
nanometer and Analog Mixed Signal (A/MS) design verification
accuracy, and R3D for analysis that leads to improvements in the
reliability and efficiency of semiconductor power devices.  
Target applications include SOC, memory, Analog Mixed Signal (A/MS),
image sensor, power device and high-speed designs.  
About Silicon Frontline
 Silicon Frontline Technology, Inc. provides
post-layout verification software that is Guaranteed Accurate and
works with existing design flows from major EDA vendors. Using new 3D
technology, the company's software products improve silicon quality
for standard and advanced nanometer processes. For more information
please visit www.siliconfrontline.com. For sales or general
assistance, please email info@SiliconFrontline.com. 
All trademarks and tradenames are the property of their respective
holders. 
Press Contact: 
Georgia Marszalek
ValleyPR LLC
+1 650 345 7477
Georgia@ValleyPR.com 
 
 
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