Freescale Semiconductor Uses Cadence Encounter RTL-to-GDSII Flow to Tapeout a 28nm 1.8GHz Communications Processor

Freescale Semiconductor Uses Cadence Encounter RTL-to-GDSII Flow to Tapeout a 
28nm 1.8GHz Communications Processor 
Encounter Digital Implementation System Significantly Boosts
Performance, Reduces Density, and Turnaround Time 
SAN JOSE, CA -- (Marketwired) -- 08/15/13 --  Cadence Design Systems,
Inc. (NASDAQ: CDNS), a leader in global electronic design innovation,
today announced that Freescale(R) Semiconductor used the latest
release of Encounter(R) Digital Implementation (EDI) System to
tapeout its next generation QorIQ(R) T4240 system on chip (SoC)
running at 1.8 GHz. The T4240 is based on multiple 64-bit Power
Architecture(R) clusters of high-performance e6500 processors and
modern system peripherals.  
Freescale's QorIQ processing platforms are complete SoCs for
networking applications across carrier, enterprise cloud computing,
military, and industrial markets. The highly integrated T4240 SoC has
a complex floorplan with multiple hierarchical blocks, 12 Power
Architecture 64-bit processors, high-speed I/O, on-chip networking,
high-speed cache coherency interconnect fabric, and complex clocking
schemes, requiring high performance and power efficiency.  
"Our T4240 SoC represents a great step forward in our
high-performance QorIQ T series product line targeted for demanding
networking applications. Cadence's GigaOpt technology helped us
achieve aggressive time to market for our next generation T4240 SoC,"
said Ken Hansen, vice president and chief technology officer,
Freescale Semiconductor. "We were also able to realize better design
performance, smaller silicon area, and improve design team
productivity." 
GigaOpt is a new multi-threaded physical optimization technology
included as standard in the latest EDI System release for pre-route,
post-clock tree synthesis, and post-route optimization. GigaOpt also
includes new layer-aware timing-driven net buffering and critical
path replacement algorithms which deliver significant improvements in
design performance, area, and power.  
"We are committed to developing innovative technologies that address
the most demanding design challenges facing the industry," said Dr.
Chi-Ping Hsu, chief strategy officer, EDA, and senior vice president,
Digital and Signoff Group at Cadence. "Freescale has be
en a great
partner to Cadence and we are pleased to see GigaOpt bring such
significant performance and schedule improvements to Freescale's
state-of-the-art SoC designs." 
Learn more about Encounter Digital Implementation here.  
About Cadence 
Cadence enables global electronic design innovation and plays an
essential role in the creation of today's integrated circuits and
electronics. Customers use Cadence software, hardware, IP, and
services to design and verify advanced semiconductors, consumer
electronics, networking and telecommunications equipment, and
computer systems. The company is headquartered in San Jose, Calif.,
with sales offices, design centers, and research facilities around
the world to serve the global electronics industry. More information
about the company, its products, and services is available here.  
Cadence, Encounter and the Cadence logo are registered trademarks of
Cadence Design Systems, Inc. in the United States and other
countries. All other trademarks are the property of their respective
owners. 
For more information, please contact:
Dean Solov
Cadence Design Systems, Inc.
408-944-7226
dsolov@cadence.com 
 
 
Press spacebar to pause and continue. Press esc to stop.