MEDIA ALERT: Cadence Celebrates 25 Years as a Leader in the EDA Industry at 50th DAC SAN JOSE, CA -- (Marketwired) -- 05/23/13 -- Cadence Design Systems, Inc. (NASDAQ: CDNS) WHO: Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, will demonstrate the latest advancements and solutions to key technology challenges, solved in collaboration with customers and partners, at Design Automation Conference (DAC) 2013. WHEN: Sunday, June 2 through Thursday, June 6, 2013 WHERE: DAC 2013 will take place at the Austin Convention Center in Austin, Texas. WHAT: -- Join Cadence and its partners in celebrating 25 years of driving the future of innovation at DAC. -- Cadence executives will be onsite to answer any inquiries about the newly launched Cadence(R) Tempus(TM) Timing Signoff Solution. Learn more about how it can yield up to 10X faster performance than traditional timing analysis solutions. -- Attend a series of Cadence-hosted breakfasts and luncheons where technology experts, industry veterans, and Cadence customers share their visions for solving some of the industry's toughest challenges. The seminars will be held in the Austin Convention Center, Level 4, Ballrooms E and F. To register, click here. -- Monday, June 3 Luncheon: Has "Timing Signoff Innovation" Become an Oxymoron? What Happened and How Do We Fix It? Time: 11:30 AM - 1:30 PM Location: Austin Convention Center, Fourth Floor, Ballrooms E and F -- Tuesday, June 4 Breakfast - The Cadence System-to-Silicon Verification Breakfast Time: 8:00 AM - 10:00 AM Location: Austin Convention Center, Fourth Floor, Ballrooms E and F Moderator: Brian Fuller, Cadence Panelists: Mihir Pandya, Freescale Avi Ziv, IBM Alex Starr, AMD Mike Stellfox, Cadence -- Tuesday, June 4 Luncheon - Panel: FinFETs - Challenges in Deployment Time: 11:30 AM - 1:30 PM Location: Austin Convention Center, Fourth Floor, Ballrooms E and F Moderator: Brian Fuller, Cadence Panelists: Suk Lee, TSMC Anthony Hill, Texas Instruments John Heinlein, ARM Chi-Ping Hsu, Cadence -- Wednesday June 5 Breakfast - Unique challenges posed by coherent SoC interconnects: verifying hardware-managed coherency and analyzing performance Time: 8:00 AM - 10:00 AM Location: Austin Convention Center, Fourth Floor, Ballrooms E and F Speakers: William Orme, ARM Avi Behar, Cadence Stewart Penman, Cadence -- A variety of live presentations will take place in booth #2214, featuring real-world solutions to help design teams innovate and succeed. -- Cadence Technology Sessions provide in-depth presentations and demonstrations of technologies and methodologies to help designers realize the highest-quality silicon, system-on-chip devices, and complete systems at lower costs. Click here for the full schedule. -- Cadence will also have a Theater highlighting customer and partner successes using Cadence products and technologies. -- Join industry colleagues at the annual Denali Party by Cadence. Don't forget to register for the party here and pick up your party wristband before noon on June 4 at the Cadence booth #2214. -- Tuesday, June 4 Time: 8:00 PM to 12:30 AM Location: Maggie Mae's, 323 East 6th St., Austin Acomplete listing of Cadence activities at DAC can be found here. About Cadence Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com. For more information, please contact: Mariel Firmacion Cadence Design Systems, Inc. (408) 944-7039 email@example.com
MEDIA ALERT: Cadence Celebrates 25 Years as a Leader in the EDA Industry at 50th DAC
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