Cadence Introduces the Tempus Timing Signoff Solution, Delivering Unprecedented Performance and Capacity in Design Closure and

Cadence Introduces the Tempus Timing Signoff Solution, Delivering Unprecedented 
Performance and Capacity in Design Closure and Signoff 
SAN JOSE, CA -- (Marketwired) -- 05/20/13 --  Cadence Design Systems,
Inc. (NASDAQ: CDNS) 
HIGHLIGHTS:  


 
--  The Tempus Timing Signoff Solution yields up to an order of magnitude
    faster performance than traditional timing analysis solutions
--  Scalable to handle full flat analysis of designs in the hundreds of
    millions of instances
--  Integrated signoff closure environment leverages innovative
    physically-aware ECO technology to accelerate design closure by weeks

  
In a move to ease and speed the development of complex ICs, Cadence
Design Systems, Inc. (NASDAQ: CDNS) today introduced the Tempus(TM)
Timing Signoff Solution, a new static timing analysis and closure
tool designed to enable System-on-Chip (SoC) developers to speed
timing closure and move chip designs to fabrication quickly. The
Tempus Timing Signoff Solution represents a new approach to timing
signoff tools that enables customers to shrink timing signoff closure
and analysis for faster tapeout while producing designs with less
pessimism, area and power consumption. 
"At Cadence, our mission is to help our customers build great,
winning products," said Lip-Bu Tan, president and chief executive
officer at Cadence. "Achieving design closure on today's complex SoCs
is a significant challenge to hitting market windows. We developed
the Tempus Timing Signoff Solution in collaboration with customers
and ecosystem partners to address this challenge."  
The new capabilities introduced in the Tempus Timing Signoff Solution
include:  


 
--  The first massively distributed parallel timing engine on the market
    which can scale to utilize up to hundreds of CPUs.
--  Parallel architecture enables the Tempus Timing Signoff Solution to
    analyze designs in the hundreds of millions of instances without
    compromising accuracy.
--  A new path-based analysis engine that leverages multi-core processing
    to reduce pessimism. With its performance advantage, the Tempus Timing
    Signoff Solution enables broader use of path-based analysis than other
    solutions.
--  Multi-mode, multi-corner (MMMC) analysis and physically-aware timing
    closure that leverages multi-threaded and distributed timing analysis.

  
The Tempus Timing Signoff Solution advanced capabilities can handle
designs containing hundreds of millions of cell instances without
compromising accuracy. Initial engagements with customers have shown
that the Tempus Timing Signoff Solution can achieve timing closure in
days on a design that would have taken several weeks with traditional
flows. 
"Today, the time spent in timing closure and signoff is approaching
40 percent of the overall design implementation flow. Traditional
signoff flows have failed to keep pace with the increasing demands of
achieving timing closure on complex designs," said Anirudh Devgan,
corporate vice president, Silicon Signoff and Verification, Silicon
Realization Group at Cadence. "The Tempus Timing Signoff Solution
represents a significant advancement in timing signoff tool
innovation and performance, leveraging multi-processing and ECO
features to achieve signoff faster than with traditional flows." 
"We are pleased to see new capabilities in the area of static timing
analysis (STA) from Cadence," said Sanjive Agarwala, director of
processor development, Texas Instruments. "As we move to more
advanced process nodes, timing closure becomes more difficult. It's
great to see Cadence taking on this challenge by offering new
technology designed to tackle tough design closure issues."  
Availability 
The Tempus Timing Signoff Solution is expected to be available in the
third quarter of 2013. Cadence plans to showcase the tool's advanced
capabilities at DAC, June 3-5, 2013 in Austin, Texas. For more
information about Tempus Timing Signoff Solution, please click here. 
About Cadence 
Cadence enables global electronic design innovation and plays an
essential role in the creation of today's integrated circuits and
electronics. Customers use Cadence software, hardware, IP, and
services to design and verify advanced semiconductors, consumer
electronics, networking and telecommunications equipment, and
computer systems. The company is headquartered in San Jose, Calif.,
with sales offices, design centers, and research facilities around
the world to serve the global electronics industry. More information
about the company, its products, and services is available at
www.cadence.com. 
Cadence and the Cadence logo are registered trademarks and Tempus is
a trademark of Cadence Design Systems, Inc. in the United States and
other countries. All other trademarks are the property of their
respective owners. 
For more information, please contact:
Dean Solov
Cadence Design Systems, Inc.
408-944-7226
dsolov@cadence.com 
 
 
Press spacebar to pause and continue. Press esc to stop.