Altera Cyclone V GT FPGA Is Industry's First Low-Power FPGA to Achieve
Compliance for PCIe Gen2 at 5 Gbps
Industry's Only Low-power 28 nm FPGA in Production Allows Developers to Reduce
Total System Costs in PCIe Gen2 Applications
SAN JOSE, Calif., March 18, 2013
SAN JOSE, Calif., March 18, 2013 /PRNewswire/ --Altera Corporation (NASDAQ:
ALTR) today announced its 28 nm Cyclone® V GT FPGA completed compliance
testing with the PCI Express^® (PCIe^®) 2.0 specification. Available in
production today, the Cyclone V GT FPGA is the industry's first low-cost,
low-power FPGA to achieve PCIe 2.0 interoperability with data rates of 5 Gbps.
The Cyclone V GT FPGA successfully passed all PCI-SIG^® compliance and
interoperability tests at the most recent PCI-SIG workshop and is currently
included on the PCI-SIG Integrators List. Cyclone V GT FPGAs provide
developers a significant reduction in system costs and system power when
developing PCIe Gen2-based applications compared to previously available
"Achieving PCIe Gen2 compliance with our Cyclone V GT FPGA marks another
milestone in the successful rollout of our 28 nm Cyclone V FPGA family," said
Sabrina Raza, senior product marketing manager at Altera. "Customers who need
the system performance offered by PCIe Gen2 now have the ability to use a
low-power FPGA and lower their total system costs. Leveraging our expertise in
transceiver technology and our proficiency in developing PCIe design
solutions, we allow customers to save a significant amount in system costs
while not trading off on performance."
Cyclone V FPGAs feature integrated transceivers with data rates up to 5 Gbps
and have two hardened PCIe IP blocks embedded within the device. The PCIe hard
IP blocks enable developers to increase system performance and system
functionality while boosting design team productivity. The PCIe 2.0-compliant
hard IP blocks consists of the PHY/MAC, data link and transaction layers. The
blocks can be configured to function as an end point or a root port and
supports up to x4 lanes.
Cyclone V FPGAs and Cyclone V SoCs have an innovative multifunction support
feature that allows up to eight PCIe end points to be combined into a single
end point while still being supported by standard device drivers. This
convenient feature benefits applications such as I/O expansion by reducing
software driver development time. The Cyclone V FPGA and Cyclone V SoC are
also equipped with Altera's innovative Configuration via Protocol using PCIe,
which allows the hard PCIe core in the devices to operate without the FPGA
fabric being loaded. This ensures the PCIe end point is ready for enumeration
under the PCIe protocol's required 100ms specification regardless of the
configuration method being used.
Altera offers a full spectrum of PCI-SIG-compliant solutions across its entire
product portfolio that are optimized to meet key application requirements.
These solutions include configurable PCIe intellectual property (IP) cores and
development boards for endpoint, bridge, switch and root port functionalities.
Altera's latest Cyclone V GT FPGA Development Kit enables simple and fast PCIe
Gen2 protocol implementation while reducing design risk and shortening
development times. The development kit provides a quick and simple approach to
develop low-cost and low-power FPGA system-level designs to achieve rapid
Cyclone V GT FPGAs are currently in production. Altera offers the broadest
portfolio of 28 nm low-power, low-cost FPGAs in the industry, with densities
ranging from 25K logic elements (LEs) to 300K LEs and the smallest form factor
packaging options that are tailored to customer's needs. For more information
about Altera's Cyclone V GT FPGAs, visit www.altera.com/cyclone5. To learn
more about the PCIe capabilities featured in Altera's FPGAs, visit
Altera® programmable solutions enable system and semiconductor companies to
rapidly and cost effectively innovate, differentiate and win in their markets.
Find out more about Altera's FPGAs, SoCs, CPLDs and ASICs at www.altera.com.
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SOURCE Altera Corporation
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