CEVA Introduces MUST™ Multi-core System Technology, Adds Vector Floating-point Capabilities for CEVA-XC DSP Architecture

CEVA Introduces MUST™ Multi-core System Technology, Adds Vector Floating-point
             Capabilities for CEVA-XC DSP Architecture Framework

Architecture framework further enriched with full support for ARM® AXI4
specification, AMBA 4 ACE cache coherency and a broad range of optimized
tightly coupled extensions for wireless applications

PR Newswire

MOUNTAIN VIEW, Calif., Feb. 19, 2013

MOUNTAIN VIEW, Calif., Feb. 19, 2013 /PRNewswire/ --CEVA, Inc. (NASDAQ:
CEVA), the leading licensor of silicon intellectual property (SIP) platform
solutions and DSP cores, today announced a suite of advanced processor and
multi-core technologies to further enhance the CEVA-XC DSP architecture
frameworkfor high performance wireless applications including wireless
terminals, small cells, access points, metro and macro base-stations. Among
the new enhancements are: comprehensive multi-core features, high-throughput
vector floating-point processing and a complete set of co-processor engines
offering power-efficient hardware-software partitioning. CEVA has collaborated
closely with leading OEMs, wireless semiconductors and IP partners for the
definition and optimization of these technologies.

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J. Scott Gardner, Senior Analyst at The Linley Group, commented: "In addition
to improving performance while reducing cost and power consumption in wireless
baseband designs, the new enhancements to the CEVA-XC architecture offer SoC
designers a comprehensive environment to develop and optimize high-speed data
flow in multi-core designs. Furthermore, the use of ARM's latest interconnect
and coherency protocols, together with advanced automated data traffic
managers, as well as a dynamic scheduling software framework, position CEVA as
the only DSP licensor today offering such extensive support for multi-core
DSP-based SoCs. When combined with vectorized floating-point support and a
wide range of coprocessor engines, the CEVA-XC architecture framework includes
all the essential DSP platform components for a wide range of user equipment
and infrastructure applications."

MUST™ - advanced multi-core system technology

CEVA's MUST™ is a cache-based multi-core system technology with advanced
support for cache coherency, resource sharing and data management. Initially
available for the CEVA-XC, MUST™ supports the integration of multiple CEVA-XC
DSP cores in a symmetric multiprocessing or asymmetric multiprocessing system
architecture, along with a broad range of technologies designed specifically
for multi-core DSP processing. These technologies include:

  oDynamic scheduling using shared pools of tasks,
  oHardware event based scheduling defined via software,
  oTask and data driven shared resource management,
  oAdvanced memory hierarchy support with full cache coherency,
  oAdvanced automated data traffic management without software intervention,
    and
  oSpecial prioritization scheme based on task-awareness.

To facilitate the development of advanced multi-core SoCs containing ARM®
processors and multiple CEVA DSPs, CEVA has added extensive support to the
CEVA-XC architecture framework for the ARM AXI4 interconnect protocol and AMBA
4 ACE cache coherency extensions. This dramatically simplifies the software
development and debugging process for SoC designs, while also reducing the
software cache management overhead, processor cycles and external memory
bandwidth. The overall outcome is much tighter integration between the
processors in the SoC, resulting in improvements in energy-efficiency and
performance for the entire system.

Full support for vectorized floating-point operations

The LTE-Advanced and 802.11ac standards leverage multiple input multiple
output (MIMO) processing, where the system utilizes multiple antennae to
transmit and receive data. In order to achieve ultra-high precision and
optimal performance when processing these complex data streams, CEVA has added
support for floating-point operations to the CEVA-XC vector processor unit, in
addition to the traditional fixed-point capabilities. Floating-point
operations are supported on full vector elements, processing up to 32 floating
point operations in every core cycle to meet the performance requirements of
even the most demanding wireless infrastructure applications. In addition to
these enhancements, CEVA has further extended its technology leadership with a
dedicated instruction set architecture (ISA) for high-dimension MIMO,
including support for 802.11ac 4x4 use cases.

Complete set of ultra-low power coprocessors for wireless modems

To further optimize advanced wireless systems for low power and performance,
CEVA has introduced a comprehensive set of tightly-coupled extension (TCE)
coprocessor units. These coprocessors address functions of the modem where
greater performance can be achieved through the use of hardware that is
tightly coupled with the CEVA-XC. CEVA's TCEs now include:

  oMaximum Likelihood MIMO Detectors (MLD),
  o3G de-spreader units,
  oFFT with NCO phase correction,
  oDFT,
  oViterbi,
  oHARQ combining, and
  oLLR compression / de-compression

These tightly-coupled extensions are complemented by a unique automated
low-latency data traffic management between the DSP memory and the
coprocessors to minimize DSP intervention and enable a truly parallel
co-processing capability. CEVA offers these TCEs as part of fully integrated
and optimized modem reference architectures for licensees targeting user
equipment, infrastructure and Wi-Fi applications, serving to lower the overall
power consumption and significantly reduce customers' development costs and
time to market.

Eran Briman, vice president of marketing at CEVA commented: "The suite of
technologies introduced today for the CEVA-XC will serve to vastly improve the
performance, power consumption and time-to-market for multi-core DSP SoC
designs targeting wireless applications. We collaborated closely with industry
leaders in the handset and infrastructure markets throughout the specification
process, ensuring our IP exceeds the stringent specifications required by the
wireless industry. The combination of our MUST multi-core system technology,
vector floating-point operation support, full support for ARM's latest
interconnect protocols and the large set of function-specific tightly-coupled
extensions further reinforces our unrivalled leadership in DSP technologies
for communications and provides a comprehensive solution for the development
of high performance systems for LTE-Advanced, Wi-Fi and beyond."

About CEVA, Inc.

CEVA is the world's leading licensor of silicon intellectual property (SIP)
DSP cores and platform solutions for the mobile, portable and consumer
electronics markets. CEVA's IP portfolio includes comprehensive technologies
for cellular baseband (2G / 3G / 4G), multimedia (vision, imaging and HD
audio), voice processing, Bluetooth, Serial Attached SCSI (SAS) and Serial ATA
(SATA). In 2012, CEVA's IP was shipped in more than 1 billion devices,
powering smartphones from many of the world's leading OEMs, including HTC,
Huawei, Lenovo, LG, Nokia, Motorola, Samsung, Sony, TCL and ZTE. Today, more
than 40% of handsets shipped worldwide are powered by a CEVA DSP core. For
more information, visit www.ceva-dsp.com. Follow CEVA on twitter at
www.twitter.com/cevadsp.



SOURCE CEVA, Inc.

Website: http://www.ceva-dsp.com
Contact: CEVA, Richard Kingston, CEVA, Inc., +1-650-417-7976,
richard.kingston@ceva-dsp.com, or Mike Sottak, Wired Island, Ltd.,
+1-408-876-4418, mike@wiredislandpr.com