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Altera Quartus II Software Version 12.1 Accelerates System Development with Enhanced High-Level Design Flows



 Altera Quartus II Software Version 12.1 Accelerates System Development with
                       Enhanced High-Level Design Flows

Addition of Altera's SDK for OpenCL to Altera's High-level Design Flows
Improves Designer Productivity and Increases System Performance

PR Newswire

SAN JOSE, Calif., Nov. 19, 2012

SAN JOSE, Calif., Nov. 19, 2012 /PRNewswire/ -- Altera Corporation (Nasdaq:
ALTR) today announced the release of its Quartus® II software version 12.1,
the industry's number one design suite in performance and productivity for
CPLD, FPGA, SoC FPGA and HardCopy® ASIC designs. The latest version
strengthens the Quartus II software's high-level design environment by
continuing to ease traditional hardware development tasks so users can
maximize productivity while benefiting from the broad range of leading-edge
capabilities of Altera devices. Quartus II software version 12.1 bolsters its
support for high-level design flows with the inclusion of an SDK for OpenCL™,
and enhancements to both its Qsys system integration tool and DSP Builder
model based design environment. Also included in the latest software release
are several enhancements, such as a partial reconfiguration design flow, new
intellectual property (IP) cores and expanded support for 28 nm FPGAs and SoC
FPGAs. These enhancements further enable customers' to rapidly design,
implement and get to market using Altera® devices.

(Photo:  http://photos.prnewswire.com/prnh/20101012/SF78952LOGO)

Accelerating System Development with High-level Design Tools
The high-level design tools Altera offers include system-level C-based,
IP-based and model-based design entry systems. These tools support and
simplify the development of today's advanced programmable systems, which
include CPU cores, digital signal processing (DSP) blocks and multiple IP
sub-systems. The addition of an SDK for OpenCL allows system developers and
programmers familiar with C to quickly and easily develop high-performance,
power-efficient FPGA-based applications using an open high-level programming
language. The SDK for OpenCL reduces hardware design complexities and allows
software programmers familiar with C to target FPGAs.

Enhancements made to Altera's Qsys system integration tool and DSP Builder
tool provide further design productivity and system performance benefits to
users. Qsys features expanded support for industry-standard ARM® AXI3 and AXI4
protocols, and DSP Builder provides expanded support for seven different
floating point precisions, including IEEE 754 half, single and double
precision support. Further simplifying system design, the latest Quartus II
software release includes a 100G Interlaken IP core to enable high-speed
chip-to-chip packet transfers and a new video trace monitor IP core for video
processing applications.

"As FPGAs continue to integrate additional capabilities through silicon
convergence, Altera's development tools can dramatically increase designer
productivity by offering higher levels of design abstraction such as OpenCL,"
said Alex Grbic, director of software, DSP and IP marketing at Altera. "Altera
continues to be at the forefront of delivering industry-leading development
tools and IP, providing our customers with the fastest path from ideas to
implemented systems."

Included in the Quartus II software version 12.1 is the first production
release of Altera's new partial reconfiguration design flow for Stratix® V
FPGAs. Partial reconfiguration provides the flexibility to change the device's
core functionality on the fly while other portions of the FPGA design are
still running. Designers store different functions in external memory and load
them into the FPGA as needed, allowing customers to reduce the size of the
FPGA used in their system, saving board space and cost and reducing power
consumption.

The Quartus II software version 12.1 also includes a variety of additional
enhancements, including support for new devices. Several new 28 nm Stratix V,
Arria® V and Cyclone® V FPGAs and SoC FPGAs are supported in this release,
including full support for Arria V GZ FPGAs. To see a list of all the new
features in this software release, visit www.altera.com/whatsnew.

Pricing and Availability
Both the Subscription Edition and the free Web Edition of Quartus II software
v12.1 are now available for download. Altera's software subscription program
simplifies obtaining Altera design software by consolidating software products
and maintenance charges into one annual subscription payment. Subscribers
receive Quartus II software, the ModelSim®-Altera Starter edition and a full
license to the IP Base Suite, which includes 15 of Altera's most popular IP
(DSP and memory) cores. The annual software subscription is $2,995 for a
node-locked PC license and is available for purchase at Altera's eStore. The
SDK for OpenCL is currently available to customers through an early access
program by contacting your local Altera sales representative.

About Altera
Altera programmable solutions enable system and semiconductor companies to
rapidly and cost-effectively innovate, differentiate, and win in their
markets. Find out more about Altera's FPGA, CPLD and ASIC devices at
www.altera.com. Follow Altera via Twitter, LinkedIn, Facebook, YouTube and
RSS.

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX
words and logos are trademarks of Altera Corporation and registered in the
U.S. Patent and Trademark Office and in other countries. OpenCL and the OpenCL
logo are trademarks of Apple, Inc. used by permission by Khronos. All other
trademarks and service marks are the property of their respective holders as
described at www.altera.com/legal.

Editor Contact:
Steve Gabriel
Altera Corporation
(408) 544-6846
newsroom@altera.com

SOURCE Altera Corporation

Website: http://www.altera.com
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