Altera Announces Industry's First FPGA Support for OpenCL - Eases the Adoption of FPGAs for Accelerating Heterogeneous Systems

Altera Announces Industry's First FPGA Support for OpenCL - Eases the Adoption
               of FPGAs for Accelerating Heterogeneous Systems

Software Development Kit for OpenCL Enables Developers to Take Advantage of
the Performance and Power-efficiencies of FPGAs

PR Newswire

SAN JOSE, Calif., Nov. 5, 2012

SAN JOSE, Calif., Nov. 5, 2012 /PRNewswire/ -- Altera Corporation (Nasdaq:
ALTR) today announced the FPGA industry's first Software Development Kit (SDK)
for OpenCL™ (Open Computing Language) which combines the massively parallel
architecture of an FPGA with the OpenCL parallel programming model. The SDK
allows system developers and programmers familiar with C to quickly and easily
develop high-performance, power-efficient FPGA-based applications in a
high-level language. The Altera SDK for OpenCL enables FPGAs to work in
concert with the host processor to accelerate parallel computation, at a
fraction of the power compared to hardware alternatives. Altera will
demonstrate the performance and productivity benefits of OpenCL for FPGAs at
SuperComputing 2012 in booth #430.


"The industry's approach for boosting system performance has evolved over time
from increasing frequency in single-core CPUs, to using multi-core CPUs, to
using parallel processor arrays," said Vince Hu, vice president of product and
corporate marketing at Altera. "This evolution leads us to today's modern
FPGAs, which are fine-grained, massively parallel digital logic arrays
architected to execute computations in parallel. Our SDK for OpenCL enables
customers to easily adopt FPGAs and leverage the performance and power
benefits the devices provide."

Altera SDK for OpenCL Design Flow
OpenCL is an open, royalty-free standard for cross-platform, parallel
programming of hardware accelerators, including CPUs, GPGPUs and FPGAs. The
Altera SDK for OpenCL offers a unified, high-level design flow for hardware
and software development that automates the time-consuming tasks required in
typical hardware-design language (HDL) flows. The OpenCL tool flow
automatically converts OpenCL kernel functions into custom FPGA hardware
accelerators, adds interface IPs, builds interconnect logic and generates the
FPGA programming file. The SDK includeslibrariesthat link to OpenCL API
callswithin ahostprogram running on the CPU. By automatically handling
these steps, designers are able to focus their development efforts on defining
and iterating their algorithms rather than designing hardware.

The portability of the OpenCL code enables users to migrate their designs to
different FPGAs or SoC FPGAs as their application requirements evolve. With
SoC FPGAs, the CPU host is embedded into the FPGA, providing a single-chip
solution that delivers significantly higher bandwidth and lower latency
between the CPU host and the FPGA compared to using two discrete devices.

Using FPGAs to Extract Maximum Parallelism in Heterogeneous Platforms
The Altera SDK for OpenCL enables programmers to leverage the massively
parallel, fine-grained architectures featured in FPGAs to accelerate parallel
computation. Unlike CPUs and GPGPUs, where parallel threads are executed
across an array of cores, FPGAs allow kernel functions to be transformed into
dedicated, deeply pipelined hardware circuits that are multithreaded using the
concept of pipeline parallelism. Each of these pipelines can be replicated
many times to provide even more parallelism by allowing multiple threads to
execute in parallel. The result is an FPGA-based solution that can deliver >5X
performance/Watt compared to alternative hardware implementations.

Altera is working with several board partners to deliver COTS board solutions
to customers. Currently, boards from BittWare and Nallatech are designed to
support Altera OpenCL. Additional third-party boards will be supported with
future releases of the SDK.

Altera has performed a variety of benchmarks that show the productivity
savings and the performance and power efficiency gained by using an OpenCL
framework for FPGA development. Based on early benchmarks and working with
customers in a variety of markets, the SDK shaved months off one customer's
development time for their video processing application and boosted
performance by 9X versus a CPU in another customer's financial application.

The Altera SDK for OpenCL is production ready and is available to customers
through an early access program. To discover the high performance,
power-efficient acceleration that OpenCL provides with FPGAs, contact a local
Altera sales representative. For additional information regarding OpenCL and
the benefits of targeting FPGA through an OpenCL implementation, visit

About Altera
Altera® programmable solutions enable system and semiconductor companies to
rapidly and cost-effectively innovate, differentiate, and win in their
markets. Find out more about Altera's FPGA, CPLD and ASIC devices at Follow Altera via Facebook, RSS and Twitter.

words and logos are trademarks of Altera Corporation and registered in the
U.S. Patent and Trademark Office and in other countries. OpenCL and the OpenCL
logo are trademarks of Apple, Inc. used by permission by Khronos. All other
trademarks and service marks are the property of their respective holders as
described at

Editor Contact:
Steve Gabriel
Altera Corporation
(408) 544-6846

SOURCE Altera Corporation

Press spacebar to pause and continue. Press esc to stop.