Altera Introduces Serial RapidIO IP Cores to Ensure Interoperability in Next-Generation Communications Infrastructure

   Altera Introduces Serial RapidIO IP Cores to Ensure Interoperability in
                Next-Generation Communications Infrastructure

Altera and IDT Team Up to Deliver Serial RapidIO® Gen2 MegaCore® Function IP
That Interoperates up to Four Lanes at 6.25 Gbaud

PR Newswire

SAN JOSE, Calif., Oct. 31, 2012

SAN JOSE, Calif., Oct. 31, 2012 /PRNewswire/ --Altera Corporation (NASDAQ:
ALTR) today announced the availability of its new Serial RapidIO® Gen2
MegaCore® function intellectual property (IP), developed to meet the growing
demand for bandwidth in global communications infrastructure systems. The new
IP solution has successfully completed full hardware interoperability with the
latest RapidIO switch from Integrated Device Technology (IDT^®), operating at
6.25 Gbaud per lane implemented on a 28 nm Altera Stratix® V FPGA. By
verifying interoperability up front, Altera and IDT enable customers deploying
RapidIO to reduce interface debug time and focus on the core functions of
system design.

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"Serial RapidIO is the optimal interconnect for clustering networks of
peer-to-peer embedded processors, DSPs, FPGAs and ASICs," said Alex Grbic,
director of product marketing at Altera. "Communication systems are demanding
more capacity for data and voice traffic, and Altera's Serial RapidIO Gen2 IP,
interoperating at the fastest rates with IDT switches, eases the
implementation of these rapidly evolving applications."

Altera worked closely with IDT to interoperate its Serial RapidIO Gen2
MegaCore function IP with IDT's 80HCPS1848 switch in x1, x2 and x4 lane
configurations from 6.25G up to 25G of aggregate bandwidth. IDT offers an
extensive line of high-performance, low-power, low-latency Gen2 Serial RapidIO
solutions, and interoperability with these proven solutions is an important
milestone for the Serial RapidIO IP from Altera.

"IDT and Altera worked together to ensure full interoperability with our
RapidIO solutions, and we are pleased to achieve this interworking milestone,"
said Tom Sparkman, general manager and vice president of the Communications
Division at IDT. "As bandwidth requirements increase in communication systems,
our customers rely on IDT's proven RapidIO switches along with FPGAs from
vendors like Altera. The interoperability of our devices allows our customers
to design and develop systems with confidence."

About Altera Serial Rapid IO IP Cores

Altera provides a range of complete FPGA solutions for the development of
custom Serial RapidIO processing elements, bridges and switches. Device and IP
support are available for Gen1 and Gen2 interfaces up to 6.25 Gbuad in x1, x2,
and x4 lane configurations. The IP core has been designed to the latest
RapidIO Specification 2.2 providing physical, transport and logical layers
with easy-to-use maintenance and I/O system functionality, as well as
extensibility to support other functions such as message passing. The solution
includes configurable Serial RapidIO IP cores and development boards.

About Stratix V FPGAs

Stratix V FPGAs are the only FPGAs optimized on TSMC's 28 nm High Performance
(28HP) high-K metal gate (HKMG) process with more than a one speed-grade
advantage over competing devices. StratixV FPGAs are the industry's only
production monolithic devices with 28 Gbps integrated transceivers. Combined
with the added benefits of increased flexibility of partial reconfiguration
and Configuration via Protocol (CvP) using the existing PCI Express® (PCIe®)
link, Stratix V FPGAs allow designers to increase their system performance and
bandwidth while reducing power. These improvements meet the demands of
high-performance applications, including wireless base stations and military
radars.

Availability

Altera offers a complete system-level, integration-ready Serial RapidIO
solution that includes Gen1 and Gen2 Serial RapidIO MegaCore function IP,
reference designs and hardware development platforms. For access to the Altera
Serial RapidIO Gen2 MegaCore function IP, or for information about the
interoperability test report, please contact sales@altera.com.

About Altera

Altera® programmable solutions enable system and semiconductor companies to
rapidly and cost-effectively innovate, differentiate and win in their markets.
Find out more about Altera's FPGA, CPLD and ASIC devices at www.altera.com.
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ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX
words and logos are trademarks of Altera Corporation and registered in the
U.S. Patent and Trademark Office and in other countries. All other words and
logos identified as trademarks or service marks are the property of their
respective holders as described at www.altera.com/legal.

Editor Contacts:
Shannon Giusti
Altera Corporation
(408) 544-7472
newsroom@altera.com

SOURCE Altera

Website: http://www.altera.com
 
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